ROM Side Channel Attack Protection via Randomized Bit Read Order
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Solution Overview
Problem
Semiconductor chips with secret words stored in ROM are vulnerable to side channel attacks, which can detect the secret word through physical implementation information such as timing, power consumption, or electromagnetic leaks.
Innovation Solution
A system comprising a memory controller, a random number generator, and a number shuffler is used to generate a random bit read or write order, reading or writing bits multiple times with only one operation being actual, and others generating random data to obscure the secret word from attackers, and inverting bits for added security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the secret word is stored in ROM for encryption/decryption, then cryptographic functionality is provided, but the secret word becomes vulnerable to side channel attacks through physical implementation information
Solution Approach 1:
The patent applies preliminary action by pre-randomizing the bit read order and pre-generating mask values before actual secret word access. The system prepares randomized access patterns and masking sequences in advance, so that when the secret word is read, the actual bit positions and values are obscured through pre-established randomization, preventing side channel attackers from correlating physical measurements with secret bits.
Solution Approach 2:
The patent introduces intermediary elements including a random number generator and mask generator that act as mediators between the secret word storage and the cryptographic operations. These intermediaries transform the direct access to secret bits into indirect access through randomized indices and masked values, breaking the direct link between physical implementation and secret information that side channel attacks exploit.
2Object-affected harmful factors
If bits are read multiple times to obscure actual read operations, then side channel attack detection becomes difficult, but the number of read cycles increases beyond the number of bits
Solution Approach 1:
The patent applies partial or excessive action by performing more read operations than the minimum required to read all bits of the secret word. The system executes multiple read cycles with randomized bit selections, where some bits are read multiple times and others not at all in a given cycle. This excessive action creates enough operational noise to obscure the actual secret word access from side channel analysis, accepting the trade-off of reduced productivity for enhanced security.
Solution Approach 2:
The patent changes parameters of the read operation by varying the number of read cycles, the specific bits accessed in each cycle, and the timing characteristics. By dynamically changing these parameters through randomization, the system transforms the predictable, uniform read operations into variable, unpredictable access patterns that prevent side channel attackers from establishing reliable correlations between physical measurements and secret bits.
3Object-affected harmful factors
If a random bit read order is generated to secure the secret word, then the reading process becomes obscured from attackers, but additional components (random number generator, number shuffler) are required
Solution Approach 1:
The patent applies segmentation by dividing the secret word access function into separate components: the secret word storage unit, the random number generator, the number shuffler, and the read control logic. This segmentation isolates the secret word from direct access, inserting intermediate processing stages that randomize and obscure the access pattern. Each component has a specific function, and together they create a layered defense against side channel attacks while maintaining modular design.
Data Source
AI summary
A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.