ROM Cell Structure Using Stacked Gates for Secure Miniaturization
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Solution Overview
Problem
Current ROMs are not sufficiently miniaturized for smaller devices and are vulnerable to hacking techniques, lacking rewritable memory capabilities and resistance to reverse engineering.
Innovation Solution
The development of a ROM comprising e-STM type memory cells with stacked insulated gates and N-channel MOS transistors, where threshold voltage determines bit values, and a manufacturing method involving semiconductor structures and trench formation to enhance security and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If ROM size is reduced for miniaturization, then device size decreases, but security against reverse engineering deteriorates
Solution Approach 1:
The ROM is divided into multiple memory blocks (first memory block, second memory block, third memory block) with different cell structures. Some blocks use e-STM cells while others use transistor-based cells, creating structural segmentation that complicates reverse engineering while enabling miniaturization through optimized layouts in each segment.
Solution Approach 2:
Different regions of the ROM employ different memory cell structures tailored to specific functions. The e-STM cells provide high-density storage in certain areas, while transistor-based cells provide security features in other areas, creating local quality variations that enhance both miniaturization and security.
2Quantity of substance
If e-STM memory cells are used for miniaturization, then ROM density increases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct phases: forming e-STM cells in first and third memory blocks, forming transistor-based cells in second memory blocks, and selective removal of insulating layers. This segmentation allows complex structures to be built using standardized, repeatable process modules.
Solution Approach 2:
A common insulating layer is deposited over the entire structure before selective removal. This preliminary action simplifies subsequent processing by providing a unified starting point for differential cell formation, reducing the overall manufacturing complexity despite the multi-structure requirement.
3Object-affected harmful factors
If multiple memory cell structures are used to enhance security, then resistance to hacking improves, but device complexity increases
Solution Approach 1:
The ROM is segmented into functional blocks with different cell structures (e-STM and transistor-based) that can be selectively activated or deactivated. This segmentation provides security through structural complexity while maintaining manufacturing feasibility through modular design.
Solution Approach 2:
The insulating layer is deposited as a preliminary structure that is later selectively removed to create different cell types. This preliminary action simplifies the creation of multiple cell structures by using a single initial layer that can be differentially processed, reducing the overall device complexity.
Data Source
AI summary
The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.