Root Complex Read Request Routing for PCIe Latency
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Solution Overview
Problem
In computing environments using PCIe and packet-based systems, latency issues arise due to processing large and small read requests in a single pipeline, leading to increased latency and reduced DMA performance, as short control structure reads wait for previous read requests to be fully fragmented.
Innovation Solution
Implementing a root complex with discrimination logic to route read requests to separate queues based on type, prioritizing control read requests over data read requests, and using time-multiplexing to service requests simultaneously, allowing for concurrent DMA transfers without increasing adapter complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If read requests are processed in a single pipeline, then device complexity is reduced, but latency increases due to sequential processing of control and data reads
Solution Approach 1:
The patent segments the single read request pipeline into two separate queues: a first queue for control structure reads and a second queue for data reads. This segmentation allows independent processing of control and data read operations, eliminating the sequential dependency that caused latency. The discrimination logic routes read requests to appropriate queues based on whether they are control or data reads, enabling parallel processing paths.
2Speed
If control read requests are prioritized over data read requests, then control structure access speed improves, but device complexity increases due to priority arbitration mechanisms
Solution Approach 1:
The patent applies local quality by assigning different service priorities to different types of read requests based on their specific needs. Control structure reads, which require low latency for system operation, are assigned high priority in the first queue. Data reads, which can tolerate more latency, are assigned lower priority in the second queue. This localized quality differentiation optimizes system response without requiring complex global arbitration mechanisms.
3Loss of time
If separate queues are used for control and data reads, then latency is reduced through parallel processing, but device complexity increases due to discrimination and arbitration logic
Solution Approach 1:
The discrimination logic performs preliminary classification of read requests before they enter the queue system. By examining predetermined fields in incoming read requests and determining their type (control or data) in advance, the system routes them to the appropriate queue before processing begins. This preliminary action prevents misrouting and reduces the need for complex arbitration during active processing, as each queue's purpose is predetermined.
Data Source
AI summary
Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request.