Rotary Clock ADC Timing for High-Speed Low-Power Conversion
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Solution Overview
Problem
Existing single-slope ADCs are limited by the speed of their counters, requiring impractically high speeds and power consumption, especially at high conversion rates like 1 Gsps, making them unfeasible with current technology.
Innovation Solution
The use of a multiphase rotary clock allows for effective 1 THz time resolution at low power by employing multiple taps of the rotary clock and building a Time-to-Digital converter, enabling 2 Gsps, 8 or 9 bit ADC operation with 4 GHz input bandwidth on standard CMOS, while reducing power consumption and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fast-running counter is used to achieve high conversion rates (1 Gsps), then the ADC speed is improved, but the power consumption becomes excessively high and the device complexity increases to impractical levels
Solution Approach 1:
The patent segments the conversion process into two distinct phases: a sampling phase where the analog input is captured and held, and a conversion phase where the held value is converted to digital. This segmentation allows the use of a slow counter during the sampling phase and only activates the conversion process when needed, dramatically reducing average power consumption while maintaining high effective conversion rates through interleaved operation of multiple channels.
Solution Approach 2:
The patent employs periodic sampling and conversion cycles, where the ADC operates in discrete intervals rather than continuously. The sample and hold circuit captures inputs periodically, and the counter increments only during designated conversion windows. This periodic operation allows the system to achieve high peak conversion rates while maintaining low average power consumption, as the high-speed counter operates only during brief conversion intervals rather than continuously.
2Measurement precision
If a 1 THz counter is constructed to achieve 1 Gsps conversion with 10 bits resolution, then the measurement precision is improved, but the device complexity and feasibility become problematic
Solution Approach 1:
The patent divides the 10-bit conversion into multiple smaller steps performed by a practical-frequency counter. Instead of requiring a single 1 THz counter to count through all 1024 states, the conversion is segmented into multiple phases where the counter operates at achievable frequencies, with the sample and hold circuit maintaining the input value throughout the extended conversion period. This segmentation makes the counter implementation feasible with current technology.
Solution Approach 2:
The sample and hold circuit performs preliminary action by capturing and storing the analog input value before the conversion process begins. This preliminary sampling allows the conversion to proceed at a slower, more manageable pace without risking loss of the input signal, enabling the use of a lower-frequency counter while still achieving high effective conversion rates through efficient use of the held value.
3Productivity
If the counter speed is increased to achieve higher conversion rates, then the productivity is improved, but the loss of time for each conversion cycle decreases, creating a trade-off
Solution Approach 1:
The patent maintains continuity of useful action by keeping the sample and hold circuit continuously ready to capture inputs, while the conversion process operates in synchronized intervals. The held value remains stable throughout the conversion cycle, allowing the counter to operate at its optimal speed without rushing, yet the system achieves high effective conversion rates by continuously preparing the next sample while the current conversion completes.
Data Source
AI summary
System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate.