Rotary Multiplexer TDM Circuitry Routing Reduction
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Solution Overview
Problem
Existing time division multiplexing (TDM) circuitry in high-speed interconnectivity systems faces inefficiencies due to increased data widths requiring numerous routings to memory elements, leading to complex and costly implementations.
Innovation Solution
The implementation of a TDM circuitry using first and second rotary multiplexers and a memory circuit, where N-bit wide data is rotated and stored, and then outputted serially, reducing the number of routings to approximately 4N, thereby simplifying data processing and transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data width is increased to achieve high-speed interconnectivity, then the data transmission capacity is improved, but the number of routings to memory elements increases significantly
Solution Approach 1:
The patent segments the N-bit wide data into multiple smaller M-bit wide data sets (where N/M is an integer). This segmentation allows the data to be processed in manageable chunks through the rotary multiplexers, reducing the routing complexity from O(N) to O(N/M) while maintaining the overall data transmission capacity.
Solution Approach 2:
The patent introduces a temporal dimension through time division multiplexing. Instead of routing all N bits simultaneously through memory elements, the system routes M-bit segments sequentially in time slots. This transforms the routing problem from a spatial complexity issue to a temporal management issue, reducing the number of simultaneous routings required.
2Device complexity
If the number of routings is reduced to simplify the circuit implementation, then the device complexity is decreased, but the data processing efficiency may be compromised
Solution Approach 1:
The rotary multiplexers continuously process data through sequential rotation operations. The first rotary multiplexer continuously rotates M-bit data segments, and the second rotary multiplexer continuously extracts and rotates k-th bits. This continuous operation maintains high data processing efficiency while using a reduced number of routings, as the system leverages temporal continuity rather than requiring all possible simultaneous routings.
Solution Approach 2:
The system performs preliminary rotation and reordering of data segments before they reach the memory elements. By pre-processing the data structure through the rotary multiplexers, the system prepares the data in an optimized format that reduces the need for complex routing operations during memory access, thereby simplifying the overall circuit implementation.
3Productivity
If direct coupling between data links and memory elements is used, then the routing efficiency is improved, but the scalability with increased data width deteriorates
Solution Approach 1:
The patent introduces dynamic reconfiguration through the rotary multiplexers that can adaptively route different M-bit data segments to different memory elements based on the current data width requirements. This dynamic capability allows the system to scale from smaller to larger data widths by adjusting the segmentation and routing patterns, making the system adaptable to varying data widths while maintaining routing efficiency.
Solution Approach 2:
The rotary multiplexer structure serves multiple functions: it segments data, reorders data segments, and routes them to appropriate memory elements. This multi-functionality allows the same circuit structure to handle various data widths (N-bit where N is a multiple of M) without requiring separate dedicated routing paths for each width, thereby improving scalability and adaptability.
Data Source
AI summary
TDM circuitry that includes a rotary multiplexer and a memory circuit is provided. A first rotary multiplexer circuit may receive N-bit wide data in accordance to a time division multiple access (TDMA) scheme. The N-bit wide data includes multiple sets of M-bit wide data. The first rotary multiplexer may rotate these sets of the M-bit wide data. The memory circuit is coupled to the first rotary multiplexer circuit. The memory circuit stores each of rotated set of M-bit wide data. A second rotary multiplexer circuit may read k-th bits of the each of the stored M-bit wide data from the memory circuit and may rotate these k-th bits before outputting these k-th bits serially, where k is an integer having a value greater than 0.