Rotary Resonant Clock Architecture for Low-Skew GPU Timing

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Solution Overview

Problem

Existing clocking architectures in graphics processing units (GPUs) face challenges with clock design complexity due to multi-die, multi-process, and low latency requirements, necessitating a robust, low-power, low-skew, and low-jitter solution that can be scaled across various product segments.

Innovation Solution

Implementing resonant rotary clocking architectures using rotary traveling wave oscillators (RTWOs) and oscillator arrays (ROAs) with fractional dividers and custom reset synchronizers, distributed across backside metal layers, to generate and distribute low-skew, low-jitter, and low-power clocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional clocking architectures are used in GPUs, then clock distribution can be implemented, but clock design complexity increases exponentially due to multi-die, multi-process, and large synchronous domain requirements

Engineering Contradiction:
Improveclock distribution reliabilityVSAvoidclock design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the large graphics die into multiple smaller clock domains, each with its own resonant clock source (RTWO). This segmentation allows independent clock generation in each domain, reducing the overall complexity of clock distribution across the entire die while maintaining reliability through localized control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimensional approach by using resonant traveling wave oscillators that generate clocks in a resonant manner, adding a temporal resonance dimension to traditional spatial clock distribution. This enables deterministic same-phase clocks across large distances by leveraging resonant frequency alignment rather than traditional hierarchical distribution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If clock skew and jitter are reduced to fs order, then deterministic same-phase clocks are achieved, but device complexity increases due to resonant oscillator implementation

Engineering Contradiction:
Improveclock skew and jitter precisionVSAvoidresonant oscillator complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The resonant traveling wave oscillators are designed to self-synchronize through their inherent resonant properties. The RTWOs naturally lock to the same frequency and phase when driven by the reset signal, eliminating the need for complex external phase-locked loop circuits or skew correction mechanisms, thereby achieving fs-order precision without proportionally increasing complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the fundamental operating parameter of clock generation from traditional LC oscillation to resonant mechanical-like oscillation in the electrical domain. By utilizing the resonant frequency of the RTWO structure itself as the defining parameter, the system achieves ultra-low skew and jitter through natural resonance rather than active correction, simplifying the overall control architecture.

Inventive Principle:
Principle #35Parameter changes

3Use of energy by moving object

If low-power clocking is implemented, then power consumption is reduced, but clock signal strength and distribution capability may be compromised

Engineering Contradiction:
Improveclock power consumptionVSAvoidclock signal strength
Core Design Contradiction:
Use of energy by moving objectVSPower

Solution Approach 1:

The resonant traveling wave oscillators generate continuous sinusoidal clock signals that maintain constant amplitude and frequency throughout the distribution network. This continuous resonant action ensures that clock signals retain sufficient strength across large die areas without requiring high initial power levels, as the resonant structure naturally sustains the signal amplitude through its Q-factor.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent employs resonant vibration principles adapted to the electrical domain, where the RTWO structure oscillates at its natural resonant frequency to generate clock signals. This resonant vibration mechanism produces high-amplitude signals with minimal power input, as the resonant structure efficiently stores and releases energy, maintaining signal strength while minimizing power consumption compared to non-resonant oscillators.

Inventive Principle:
Principle #18Mechanical vibration

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution enables deterministic same-phase clocks across large graphics dies, reducing skew and jitter to the order of fs, and providing a scalable, low-power clocking solution suitable for diverse frequency requirements.

Implementation Method 1

resonant clocking architecture... resonant rotary clocking architectures... rotary traveling wave oscillators (RTWOs)... generate and distribute low-skew, low-jitter, and low-power clocks

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS20260005651A1Resonant clocking architecture
Publication Date: 2026.01.01 INTEL CORP
  • US20260005651A1 patent drawing
  • US20260005651A1 patent drawing
  • US20260005651A1 patent drawing

AI summary

A rotary oscillator array (ROA) apparatus includes a plurality of rotary traveling wave oscillators (RTWOs) configured to generate a plurality of resonant clock signals. An RTWO of the plurality of RTWOs includes a plurality of inverter cells and a fractional divider. The inverter cells are coupled in parallel to each other between two metal interconnects. The fractional divider is coupled to the two metal interconnects. The fractional divider will output a resonant clock signal of the plurality of resonant clock signals based on a reset-out signal generated by a reset-out terminal of the RTWO.