Semiconductor Package Layout With Rotated Chips and Single-Layer Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the functionality and integration of semiconductor packages increase, the number of signal lines connected to a single package has grown, making it challenging to efficiently manufacture and cost-effectively produce semiconductor packages with multiple chips, particularly when multiple chips are required to handle diverse signals and high-density sensor arrays or display panels.
Innovation Solution
A semiconductor package design where two identical semiconductor chips are mounted on a package substrate, with one chip rotated 180 degrees relative to the other, and their signal lines are disposed in a single layer, simplifying the manufacturing process and reducing thickness and costs by eliminating the need for multi-layer via connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on a single package substrate with increased signal lines, then the functionality and integration degree increase, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent applies asymmetry by rotating the second semiconductor chip 180 degrees relative to the first chip. This asymmetric arrangement allows signal lines to be disposed in a single layer rather than requiring multiple layers, thereby reducing manufacturing complexity while maintaining high functionality and integration degree
Solution Approach 2:
The patent transitions from a multi-layer signal line structure to a single-layer structure by utilizing the rotational arrangement of chips. This dimensional simplification reduces the number of layers from multiple to one, decreasing manufacturing complexity while preserving the package's adaptability and versatility
2Adaptability or versatility
If multiple semiconductor chips are mounted on a single package substrate with increased signal lines, then the functionality and integration degree increase, but the production cost increases
Solution Approach 1:
The 180-degree rotation of the second chip creates an asymmetric configuration that simplifies the signal line structure to a single layer. This reduces the number of manufacturing steps and materials required, thereby lowering production cost while maintaining the package's high functionality
Solution Approach 2:
The patent merges the signal line transmission paths into a single layer by utilizing the rotational chip arrangement. This consolidation eliminates the need for separate multi-layer structures, reducing production cost while preserving the package's adaptability and versatility
3Adaptability or versatility
If signal lines are disposed in multiple layers, then complex signal routing is achieved, but the package thickness increases
Solution Approach 1:
The asymmetric 180-degree rotation of the second chip enables all signal lines to be routed in a single layer without requiring multiple layers. This maintains complex signal routing capability while reducing package thickness by eliminating vertical layer stacking
4Adaptability or versatility
If multiple layers of signal lines are used, then signal routing flexibility is improved, but the manufacturing process complexity increases
Solution Approach 1:
The 180-degree rotational arrangement of the second chip creates an asymmetric configuration that allows flexible signal routing to be achieved in a single layer. This maintains signal routing flexibility while dramatically simplifying the manufacturing process by eliminating multi-layer fabrication steps
Data Source
AI summary
A semiconductor package includes a first semiconductor chip and a second semiconductor chip, each including first signal pads, and second signal pads disposed in a region different from that of the first signal pads. The first semiconductor chip and the second semiconductor chip are mounted on a package substrate. The package substrate includes first signal lines connected to the first signal pads and second signal lines connected to the second signal pads. The first signal lines and the second signal lines are disposed in a same layer.