Rotated Semiconductor Die Package Layout for Low Signal Skew
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Solution Overview
Problem
Conventional chip packages for high-data communication applications suffer from signal skew and signal delay, which deteriorate electrical performance, and face challenges in controlling coplanarity and warpage, particularly in large-size packages.
Innovation Solution
An electronic package design featuring a rotated semiconductor die and a metal ring, with a rotation offset angle between 30 and 75 degrees, and a partitioned substrate surface into quadrants, along with a redistribution layer and decoupling capacitors, to reduce signal skew and improve warpage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip packages are used for high-data communication applications, then the package structure is simple and easy to manufacture, but signal skew and signal delay occur which deteriorate electrical performance
Solution Approach 1:
The semiconductor die is rotated by an offset angle (e.g., 45 degrees) relative to the package substrate, creating an asymmetric configuration. This rotation optimizes the alignment between the die bond pads and substrate traces, reducing signal skew and delay while maintaining manufacturing feasibility through standardized rotation angles.
Solution Approach 2:
The patent introduces a rotational dimension to the traditional aligned configuration. By rotating the die in the planar dimension, the design optimizes signal path geometry without adding vertical complexity, effectively managing electrical performance through spatial reconfiguration.
2Quantity of substance
If large-size chip packages are used to accommodate high-speed interface circuits, then more I/O pads can be integrated, but coplanarity and warpage control become difficult
Solution Approach 1:
The package substrate is divided into multiple quadrants with the rotated die positioned to distribute I/O pads across different quadrants. This segmentation allows for better mechanical support and warpage control in each quadrant while accommodating a high total number of I/O pads through the rotated configuration.
Solution Approach 2:
The rotation offset angle is specifically optimized for different regions of the package. By positioning the die at an angle, the design achieves uniform trace lengths and signal path characteristics across different quadrants, ensuring consistent electrical performance and mechanical stability throughout the large package area.
3Ease of manufacture
If the orientation of fan-out die attachment is limited to 0, 90, or 270 degrees, then substrate trace design and fiducial mark alignment are simplified, but signal skew cannot be optimized
Solution Approach 1:
The patent changes the orientation parameter from discrete values (0, 90, 270 degrees) to a continuous parameter by introducing a rotation offset angle. This allows optimization of signal path geometry to minimize skew while maintaining ease of manufacture through standardized angle increments that are compatible with existing fabrication processes.
Data Source
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AI summary
An electronic package (1a) configured to operate at Gigabit-per-second, Gbps, data rates is disclosed. The electronic package (1a) includes a package substrate (20) of a rectangular shape. A chip package (10) having a first high-speed interface circuit die (11) is mounted on a top surface of the package substrate. The chip package (10) is rotated relative to the package substrate (20) about a vertical axis that is orthogonal to the top surface by about 45 degrees. The first high-speed interface circuit die (11) includes a first Serializer/Deserializer, SerDes, circuit block.