Rotated Grid 3D NAND Memory for High Density and Low Power
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Solution Overview
Problem
Three-dimensional (3D) memory structures face challenges in increasing bit density while minimizing the negative impacts on power consumption and operation speed due to the need for deep holes and increased number of string select lines, which lead to higher unit cell capacitance and read/write disturbances.
Innovation Solution
A memory device with a multilevel stack of conductive layers and pillars arranged on a rotated grid, allowing for a higher density of bit lines and reduced string select lines, which enables increased parallel operation, lower power consumption, and improved data rates by reducing unit cell capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of string select lines is increased to achieve higher bit density, then storage capacity is improved, but unit cell capacitance increases and read/write disturbances occur
Solution Approach 1:
The patent transitions from a planar 2D memory architecture to a three-dimensional vertical channel structure with gate-all-around cells. This dimensional change allows bit lines to be positioned above the memory plane, enabling higher bit density without proportionally increasing the number of string select lines, thus reducing unit cell capacitance and power consumption while maintaining storage capacity
2Quantity of substance
If the number of string select lines is increased to achieve higher bit density, then storage capacity is improved, but read/write disturbances increase
Solution Approach 1:
By moving bit lines to a higher dimension (above the memory plane) in the vertical channel structure, the patent achieves higher bit density without increasing string select line count, thereby reducing capacitive coupling and read disturbances that would otherwise occur with additional select lines
3Quantity of substance
If deep holes are created to increase storage capacity, then bit density is improved, but manufacturing complexity and power consumption increase
Solution Approach 1:
The vertical channel structure with gate-all-around cells repositions bit lines above the memory plane, achieving high storage capacity without requiring excessively deep hole etching. This dimensional reconfiguration reduces manufacturing complexity while maintaining improved bit density
Data Source
AI summary
Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle θ where tan(θ)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.