Rotated Memory Storage for SPI EEPROM First-Bit Read Timing
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Solution Overview
Problem
Standard SPI EEPROMs face challenges in meeting the timing requirements for the SPI normal read command, particularly in returning the first data bit quickly without introducing clock glitches or requiring additional wait states, especially when security features are added without altering the SPI protocol.
Innovation Solution
Implementing a rotated storage mechanism that stores the most significant bits of data in a separate section, allowing for early fetching and rotation of these bits to meet the SPI timing requirements, enabling the secure SPI slave device to return the first data bit promptly while maintaining security and adhering to the SPI protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the SPI EEPROM uses standard read command processing, then the device structure remains simple, but the first data bit cannot be returned within the required SPI timing
Solution Approach 1:
The patent segments the EEPROM data into two separate storage sections: a rotated storage section for storing rotated copies of data words, and a regular storage section for normal data storage. This segmentation allows the system to quickly access the most significant bit through the rotated section while maintaining standard storage in the regular section, thereby resolving the timing constraint without excessive complexity.
Solution Approach 2:
The patent performs preliminary action by pre-rotating and storing copies of data words in the rotated storage section before they are needed. This allows the system to have the most significant bit ready for immediate return when an SPI read command is received, eliminating the timing delay that would otherwise occur with standard read processing.
2Reliability
If the SPI EEPROM adds security functions, then data protection is improved, but the timing requirements for SPI normal read command become harder to meet
Solution Approach 1:
The patent introduces an intermediary mechanism - the rotated storage section - that acts as a buffer between the security processing requirements and the SPI timing requirements. This intermediary allows security functions to be implemented while maintaining the appearance of standard SPI timing to external masters, as the rotated data can be quickly provided to satisfy timing constraints.
Solution Approach 2:
The patent creates copies of data words in the rotated storage section with specific bit rotations applied. These copies serve as intermediaries that can be quickly accessed to meet SPI timing requirements while the original data remains protected in the main storage area, allowing security functions to operate without compromising timing.
3Reliability
If the SPI EEPROM uses internal clock domain, then clock glitch issues are eliminated, but synchronization with master device clock becomes problematic
Solution Approach 1:
The patent performs preliminary action by pre-processing and storing data in the rotated storage section before the actual SPI read transaction occurs. This allows the internal clock domain to complete its data preparation in advance, eliminating the need for clock synchronizers during the critical SPI timing window while maintaining clock stability.
Solution Approach 2:
The patent extracts the clock synchronization requirement from the critical data path by using the rotated storage section to hold pre-prepared data. This separation allows the internal clock domain to operate independently without requiring synchronizers, as the rotated data is already prepared and can be output directly to meet SPI timing.
Data Source
AI summary
A method for reading a first data bit from a non-volatile memory of a memory system is disclosed. The N most-significant bits are stored for each of M words in a rotated storage section. Address bits are serially received according to the clock signals. Before receiving a final address bit, a rotated word made up of the most significant bit of the M words is fetched from the rotated storage section. Address bits are serially received and rotated words are fetched until the N most-significant bits of the M words have been fetched. Then, un-rotated words are serially fetched from the non-volatile memory. Within one clock signal of the final address bit receipt, a bit is selected out of the fetched rotated words based on the received address bits. The first data bit is returned based on the selected bit and un-rotated words are returned based on the address.