Rotated Stacked Semiconductor Chips for Warpage Reduction
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Solution Overview
Problem
The increasing number of stacked semiconductor chips in packages leads to defects such as warpage and cracks due to uneven pressure distribution and overhang areas, affecting fabrication processes and production yield.
Innovation Solution
The semiconductor package design involves rotating subsequent chips on a line connecting their centers as a rotation axis, with internal angles between longitudinal directions of up to 45 degrees, and using bonding wires to connect exposed chip pads, along with adhesion layers and encapsulants to manage pressure and support, allowing for effective electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked semiconductor chips is increased, then the memory capacity is improved, but the occurrence of warpage and cracks increases due to uneven pressure distribution
Solution Approach 1:
The patent applies asymmetry by rotating each stacked chip by a specific angle (45°, 90°, or 135 degrees) relative to the chip below it, creating an asymmetric stacked configuration. This asymmetric arrangement distributes the overhang area and pressure more evenly across the stack, preventing concentration of stress at specific locations and thereby reducing warpage and cracks while maintaining high stacking density
2Quantity of substance
If semiconductor chips are made lighter and thinner, then the stacking capacity is improved, but the overhang area increases causing fabrication defects
Solution Approach 1:
By rotating chips at specific angles in the stack, the patent creates an asymmetric configuration that reduces the overhang area of each chip. This asymmetric arrangement ensures that no single location bears excessive load, thereby maintaining manufacturing precision and reducing fabrication defects even as chips become lighter and thinner
Solution Approach 2:
The patent introduces angular rotation as an additional dimensional parameter beyond simple vertical stacking. By varying the rotational angle of each chip in the stack, the patent optimizes the spatial distribution of chips and minimizes overhang area, enabling higher stacking capacity without compromising manufacturing quality
3Quantity of substance
If more chips are stacked to increase memory capacity, then the device complexity increases, but pressure distribution becomes uneven causing defects
Solution Approach 1:
The asymmetric rotational stacking pattern simplifies the overall structure by creating a regular, repeating angular pattern rather than requiring complex irregular arrangements. This systematic asymmetric configuration enables even pressure distribution across multiple stacked chips while maintaining manageable device complexity
Data Source
AI summary
A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.