Multi-chip Package With Rotated Stacked Chips
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Solution Overview
Problem
Conventional multi-chip packages require multiple data transmission/reception circuits for each memory chip, leading to increased circuit area and power consumption, as well as signal line loading and delays due to unnecessary coupling of transmission/reception circuits and through-silicon-vias.
Innovation Solution
A multi-chip package design where semiconductor chips are stacked with alternating 180-degree rotation, reducing the number of data transmission/reception circuits and signal line loading by enabling only necessary circuits through control signals, and optimizing internal voltage generation and distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data transmission/reception circuits are provided in each memory chip for multi-channel operation, then data transmission capability is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent merges the functionality of multiple data transmission/reception circuits into a single shared circuit. The single circuit in each slave chip can be selectively activated to handle multiple channels through time-division multiplexing, eliminating the need for separate physical circuits for each channel and thereby reducing circuit area while maintaining multi-channel data transmission capability
Solution Approach 2:
The patent introduces dynamic control mechanisms where a single data transmission/reception circuit can be selectively enabled or disabled based on which channel needs to operate. This dynamic activation allows the circuit to serve multiple channels at different times, providing multi-channel functionality without requiring multiple simultaneous circuits
2Productivity
If multiple data transmission/reception circuits are provided in each memory chip, then data transmission capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic activation of the data transmission/reception circuit, where the circuit is enabled only during the time period when its channel needs to transmit or receive data. Through time-division multiplexing controlled by slice ID signals, the single circuit alternates between different channels in a periodic manner, ensuring that power is consumed only when necessary rather than continuously by multiple always-on circuits
Solution Approach 2:
The patent extracts the channel identification functionality from the data transmission/reception circuit itself and implements it through external control signals (slice ID signals). This allows a single circuit to be dynamically assigned to different channels based on the control signals, eliminating the need for multiple dedicated circuits and reducing overall power consumption
3Productivity
If through-silicon-vias are used to couple multiple channels, then three-dimensional stacking is achieved, but signal line loading and delays increase
Solution Approach 1:
The patent extracts unnecessary signal line couplings by implementing selective activation of data transmission/reception circuits. By enabling only the circuit corresponding to the active channel based on slice ID signals, the patent eliminates signal line loading from inactive channels, thereby reducing overall signal line loading and associated transmission delays in the three-dimensional stacked structure
Data Source
AI summary
A multi-chip package includes first and second semiconductor chips that are sequentially stacked, each of the first and second semiconductor chips including an operation block for an internal operation, third and fourth semiconductor chips that are sequentially stacked over the second semiconductor chip and rotated 180 degrees in a horizontal direction with respect to the first and second semiconductor chips, each of the third and fourth semiconductor chips including an operation block, and through chip vias for transmitting predetermined signals between the operation blocks of the first to fourth semiconductor chips.


