Rotational Chip Stacking with Through-Silicon Vias
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Solution Overview
Problem
Conventional 3D chip assembly techniques require unique pad designs and mask patterns for each stacking level, leading to complex production control and inefficiencies due to varying yield rates, resulting in surplus parts and increased production costs.
Innovation Solution
A method involving the sequential stacking of chip layers with rotational symmetry, forming through holes to expose electrode surfaces, and filling these holes with conductive material, allowing for simplified production control and reduced design complexity across multiple stacking levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If unique pad designs and mask patterns are used for each stacking level, then interconnection requirements are met, but production control complexity increases
Solution Approach 1:
The patent applies universality by using identical pad designs and mask patterns across all stacking levels. The through-silicon via (TSV) structure serves multiple functions: it provides interconnection between different stacking levels, enables standardized manufacturing processes, and allows homogeneous integration of identical chips at various levels. This universal approach eliminates the need for unique designs per level, thereby reducing production control complexity while maintaining interconnection requirements.
2Adaptability or versatility
If unique part numbers are assigned to each stacking level, then design variations are accommodated, but production efficiency decreases
Solution Approach 1:
The patent implements homogeneity by using identical chip designs, pad layouts, and mask patterns for all stacking levels. This homogeneous integration approach allows the same manufacturing processes and quality control procedures to be applied uniformly across all levels, eliminating the need for unique part numbers and design variations. As a result, production efficiency is improved through standardized processes while still accommodating the functional requirements of 3D stacked architectures.
3Adaptability or versatility
If different yield rates are accepted for each stacking level, then design flexibility is maintained, but waste increases
Solution Approach 1:
The patent applies universality by using identical pad designs and mask patterns across all stacking levels. The through-silicon via (TSV) structure serves multiple functions: it provides interconnection between different stacking levels, enables standardized manufacturing processes, and allows homogeneous integration of identical chips at various levels. This universal approach eliminates the need for unique designs per level, thereby reducing production control complexity while maintaining interconnection requirements.
Solution Approach 2:
The patent implements homogeneity by using identical chip designs, pad layouts, and mask patterns for all stacking levels. This homogeneous integration approach allows the same manufacturing processes and quality control procedures to be applied uniformly across all levels, eliminating the need for unique part numbers and design variations. As a result, production efficiency is improved through standardized processes while still accommodating the functional requirements of 3D stacked architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies production control, reduces design workloads, and minimizes waste by enabling the use of standard tools and reducing the number of unique part numbers, thereby improving the efficiency and cost-effectiveness of chip assembly.
Implementation Method 1
forming, for at least one of the groups, a through hole into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The method includes further filling the through hole with conductive material.
Data Source
AI summary
A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.