Rough Buffer Layer for III-V on Silicon RF Loss Reduction
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Solution Overview
Problem
Group III-V semiconductor devices on silicon substrates face challenges due to band bending at the interface, leading to the formation of a two-dimensional hole gas (2DHG) with high carrier mobility, resulting in low resistance and reduced power added efficiency (PAE) for radiofrequency (RF) applications.
Innovation Solution
Incorporating a rough buffer layer with uneven top and bottom surfaces to promote carrier scattering, increasing resistance and reducing carrier mobility at the 2DHG, thereby enhancing the overall resistance and PAE of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a smooth buffer layer is used between silicon substrate and group III-V buffer structure, then carrier mobility is high and resistance is low, but power added efficiency is reduced due to low resistance at 2DHG
Solution Approach 1:
The buffer layer is intentionally formed with a rough surface topology featuring bumps and undulations instead of a smooth plane. This curvature and roughness at the interface promotes carrier scattering, increasing resistance at the two-dimensional hole gas (2DHG) to improve power added efficiency while maintaining adequate carrier transport for device operation
2Loss of energy
If the buffer layer surface is made rough to increase resistance, then power added efficiency improves, but manufacturing precision becomes more difficult
Solution Approach 1:
The deposition parameters (temperature, pressure, flow rates, doping conditions) are specifically adjusted and optimized to control the formation of surface roughness during the buffer layer growth process. By changing these parameters, the roughness is intentionally induced to achieve the desired carrier scattering effect while maintaining manufacturing control and repeatability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The rough buffer layer increases the device's resistance, improving power added efficiency from about 54% to 57% at 6 GHz and enhancing co-planar waveguide performance by reducing substrate losses.
Implementation Method 1
Incorporating a rough buffer layer with uneven top and bottom surfaces to promote carrier scattering, increasing resistance and reducing carrier mobility at the 2DHG
Data Source
AI summary
Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).