Embedded Bypass Capacitance Using Rough Conductive Films
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Solution Overview
Problem
High-speed digital circuits face challenges with power supply noise due to rapid current surges, which conventional discrete bypass capacitors struggle to handle effectively, limiting their ability to supply current and impacting signal propagation.
Innovation Solution
A component carrier with a capacitance structure comprising two electrically conductive film structures and a dielectric film structure, where the conductive films have a rough surface to increase the effective surface area, allowing for higher capacitance and reducing parasitic inductance, thereby providing a stable power supply for digital circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete bypass capacitors are used, then capacitance function is provided, but parasitic inductance increases and current supply ability deteriorates
Solution Approach 1:
The patent merges the bypass capacitor function directly into the PCB structure by integrating conductive layers and dielectric material within the board itself, eliminating the need for separate discrete capacitor components. This integration removes the parasitic inductance associated with discrete components and their connections.
Solution Approach 2:
The PCB structure serves multiple functions: it provides mechanical support, electrical interconnection, and bypass capacitance functionality simultaneously. The conductive layers and dielectric material in the PCB serve both structural/electrical purposes and energy storage purposes for high-frequency current surges.
2Reliability
If conventional FR-4 material is used between conductive layers, then capacitance is provided, but capacitance value is limited
Solution Approach 1:
The patent changes the dielectric parameter by using material with higher permittivity (εr) than conventional FR-4, such as ceramic-filled polymers or high-k dielectric materials. This increases the capacitance value (C = εA/d) without changing the physical dimensions of the PCB structure.
Solution Approach 2:
The patent creates multiple nested capacitive structures within the PCB by stacking multiple conductive layers with dielectric material between them, forming a multi-layer capacitor structure embedded within the PCB. This nested arrangement increases total capacitance while maintaining compact form factor.
3Reliability
If smooth conductive surfaces are used, then manufacturing is simple, but effective surface area is limited and capacitance is reduced
Solution Approach 1:
The patent introduces surface curvature and irregularities to the conductive layers, creating rough or textured surfaces that increase the effective surface area. This roughening effect increases capacitance by providing more surface area for electric field interaction while maintaining planar overall structure.
Solution Approach 2:
The patent employs porous or foam-like conductive structures that provide dramatically increased surface area within a compact volume. The porous structure allows for higher capacitance density while maintaining electrical conductivity and mechanical integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased capacitance ensures timely supply of current during surges, improving signal integrity and reducing unwanted noise, especially at high-frequency digital signal propagation, while also reducing layer count and cost.
Implementation Method 1
a capacitance structure (100) comprising two electrically conductive film structures (110, 120) and a dielectric film structure (130) sandwiched in between the two electrically conductive film structures
Implementation Method 2
at least the electrically conductive film structure (110) is provided with a rough surface (111) such that the effective surface for the bypass capacitance structure will be increased
Data Source
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AI summary
There is provided a component carrier (450, 550) comprising: (a) a stack (460, 560a, 560b) of at least one electrically conductive layer structure (464, 468) and at least one electrically insulating layer structure (462, 466); and (b) a bypass capacitance structure (100, 300) formed on an/or within the stack (460, 560a, 560b). The bypass capacitance structure (100, 300) comprises an electrically conductive film structure (110) having a rough surface (111a), a dielectric film structure (130) formed on the rough surface (111a), and a further electrically conductive film structure (120, 320) formed on the dielectric film structure (130).