Roughened Alignment Mark for Wiring Substrate Optical Recognition

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Solution Overview

Problem

The existing wiring substrates with flat alignment marks face challenges in properly aligning semiconductor chips due to diffused reflection issues, making it difficult to recognize the alignment marks during the mounting process.

Innovation Solution

A wiring substrate with a roughened alignment mark face, having a surface roughness between 50 nm and 200 nm, is developed, allowing for improved diffused reflection and easier recognition using optical alignment methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the alignment mark face is made flat, then the manufacturing process is simple, but the light reflection is insufficient leading to poor recognition

Engineering Contradiction:
Improvelight reflectionVSAvoidsurface processing complexity
Core Design Contradiction:
Illumination intensityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the surface roughness parameter of the alignment mark face. Specifically, the surface roughness is controlled within the range of 50 nm to 200 nm to optimize light reflection for machine vision recognition while maintaining manufacturing feasibility through electrolytic plating process control

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the alignment mark face is roughened to improve light reflection, then recognition is improved, but the manufacturing precision becomes more difficult to control

Engineering Contradiction:
Improvealignment recognition precisionVSAvoidsurface roughness control
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent establishes specific parameter ranges for surface roughness (50 nm to 200 nm) that balance recognition performance with manufacturing control. This parameter optimization allows standard electrolytic plating processes to achieve the required roughness without requiring complex additional processing steps

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent incorporates surface roughness control into the electrolytic plating process itself, performing the roughening action during the initial wiring layer formation rather than as a separate subsequent step. This preliminary action simplifies the overall manufacturing process while achieving the desired surface characteristics

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The roughened alignment mark surface enhances the visibility and recognition during the alignment process, ensuring accurate mounting of semiconductor chips on the wiring substrate.

Implementation Method 1

The roughened alignment mark surface enhances light reflection, enabling easier recognition and accurate alignment of semiconductor chips

Methodology Applied
Scientific EffectLight reflection: Reflection

Data Source

PatentUS8673744B2Wiring substrate, manufacturing method thereof, and semiconductor package
Publication Date: 2014.03.18 SHINKO ELECTRIC IND CO LTD
  • US8673744B2 patent drawing
  • US8673744B2 patent drawing
  • US8673744B2 patent drawing

AI summary

A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.