Roughened Conductive Pillars for Semiconductor Package Adhesion

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The interface between conductive pillars and other materials in semiconductor packages is prone to delamination and cracking due to thermal mismatch and mechanical stress, leading to reliability and performance issues during thermal cycling and stress testing.

Innovation Solution

The method involves creating a semiconductor package structure with conductive pillars that have roughened sidewalls featuring protruded portions and notches, increasing the surface roughness and contact area with other materials, thereby enhancing adhesion and reducing the likelihood of delamination or cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If smooth-walled conductive pillars are used, then the manufacturing process is simple, but the adhesion between conductive pillars and other materials is poor leading to delamination and cracking

Engineering Contradiction:
Improveadhesion strengthVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive pillar sidewalls are transformed from smooth planar surfaces to rough surfaces with protruded portions and notches. This curvature and irregularity increases the surface area and creates mechanical interlocking with adjacent materials, significantly improving adhesion strength and preventing delamination during thermal cycling.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The conductive pillar sidewalls incorporate a porous or rough structure with protrusions and notches rather than a smooth surface. This porous morphology increases the effective contact area and creates anchor points for adjacent materials, enhancing interfacial bonding and resistance to thermal stress.

Inventive Principle:
Principle #31Porous materials

2Reliability

If conductive pillars with rough sidewalls are manufactured, then adhesion is enhanced, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveinterface stabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The rough surface structure with protrusions and notches is formed on the conductive pillar sidewalls during the pillar formation process itself, before subsequent packaging steps. This preliminary structuring ensures that the enhanced adhesion morphology is already in place to withstand subsequent thermal cycling and stress testing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The surface morphology parameter of the conductive pillar sidewalls is changed from smooth to rough with specific protrusion and notch dimensions. This parameter modification is achieved through controlled deposition or etching processes that create the desired surface topology, improving adhesion without requiring entirely new manufacturing approaches.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The enhanced adhesion between the conductive pillars and other materials, such as underfill and dielectric layers, effectively reduces or avoids delamination and cracking, improving the reliability and performance of semiconductor packages under stress testing and thermal cycles.

Implementation Method 1

the light beam is scattered by the uneven surface

Methodology Applied
Scientific EffectLight scattering: Scattering

Data Source

PatentUS10037973B2Method for manufacturing semiconductor package structure
Publication Date: 2018.07.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10037973B2 patent drawing
  • US10037973B2 patent drawing
  • US10037973B2 patent drawing

AI summary

A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.