Wiring Substrate Surface Roughening for Stable Via Connections

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Solution Overview

Problem

The connection reliability between vias and connection terminals on wiring substrates is insufficient due to undercut issues caused by isotropic etching, leading to unstable electrical connections and potential short circuits.

Innovation Solution

A wiring substrate with a laminated structure featuring a smoothed and roughened surface on the insulating layer, where the roughened portion has increased surface roughness to reduce side etching and undercut, and a method involving laser beam machining and desmear processing to form opening portions and seed layers, followed by electrolytic plating and controlled etching to minimize seed layer removal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the etching time is extended to remove all seed layer in the thickness direction, then the seed layer in unneeded portions is completely removed preventing short circuits, but side etching increases causing increased undercut

Engineering Contradiction:
Improveseed layer removal completenessVSAvoidconnection reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent changes the surface condition parameter of the insulating layer from smooth to roughened. This parameter change affects the etching process by reducing side etching of the seed layer, thereby decreasing undercut while maintaining complete seed layer removal in unneeded portions, thus resolving the contradiction between manufacturing precision and connection reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary action by roughening the surface of the insulating layer before forming the seed layer. This preliminary surface treatment modifies the etching behavior during subsequent processing, preventing excessive side etching and undercut formation while ensuring complete seed layer removal where needed

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the etching time is shortened to reduce undercut, then side etching is reduced, but the seed layer in unneeded portions is not sufficiently removed risking short circuits

Engineering Contradiction:
Improveconnection reliabilityVSAvoidseed layer removal completeness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the surface condition parameter of the insulating layer from smooth to roughened. This parameter change creates a surface morphology that suppresses side etching, allowing shorter etching times to be used while still achieving complete seed layer removal in unneeded portions, thus resolving the contradiction between connection reliability and manufacturing precision

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary action by roughening the surface of the insulating layer before seed layer formation. This preliminary treatment modifies the subsequent etching process to minimize lateral erosion, enabling sufficient seed layer removal with reduced etching time and preventing short circuits while maintaining connection reliability

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces undercut and improves connection reliability by minimizing side etching, stabilizing the electrical connection between vias and connection terminals, thereby enhancing the overall reliability of the wiring substrate.

Implementation Method 1

forming opening portions by performing laser beam machining on the insulating layer

Methodology Applied
Scientific EffectLaser heating: Laser

Implementation Method 2

forming a seed layer by performing an electroless plating on the surface of the insulating layer

Methodology Applied
Scientific EffectElectroless plating: Chemical Bonding

Implementation Method 3

performing the electrolytic plating on the seed layer

Methodology Applied
Scientific EffectElectrolytic plating: Electrodeposition

Data Source

PatentUS11997787B2Wiring substrate and method of manufacturing wiring substrate
Publication Date: 2024.05.28 SHINKO ELECTRIC IND CO LTD
  • US11997787B2 patent drawing
  • US11997787B2 patent drawing
  • US11997787B2 patent drawing

AI summary

A wiring substrate includes: a wiring layer; an insulating layer that is laminated on the wiring layer; an opening portion that passes through the insulating layer to the wiring layer; and an electric conductor film that is formed at the opening portion of the insulating layer. A surface of the insulating layer includes a smoothed portion that is not covered by the electric conductor film, and a roughened portion that includes an inner wall surface of the opening portion covered by the electric conductor film and that have surface roughness that is greater than surface roughness of the smoothed portion.