Round-Free Cryptographic Hash Circuit for Low-Latency Communications
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Solution Overview
Problem
Conventional cryptographic hash functions, which rely on multiple rounds of processing, introduce significant latency in communications, particularly in low-latency systems like vehicle-to-vehicle networks, and increasing security through more internal states and rounds exacerbates this issue.
Innovation Solution
Implementing asynchronous, un-clocked cryptographic hash circuits that operate on input data blocks without iterative rounds, using a large number of internal states connected in feedback loops with non-linear equations, ensuring quick output without clocking mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple rounds of processing are used in cryptographic hash functions, then security is improved, but latency increases
Solution Approach 1:
The patent segments the cryptographic hash function into multiple parallel processing paths, each handling a portion of the input data. Instead of sequentially processing data through multiple rounds, the invention divides the computation into independent segments that can be processed simultaneously, reducing the overall latency while maintaining security through the combined output of all segments.
Solution Approach 2:
The patent transitions from a time-dimensional approach (sequential rounds) to a spatial-dimensional approach (parallel processing paths). By adding spatial dimensionality with multiple concurrent processing channels, the system achieves both high security (through comprehensive processing) and low latency (through simultaneous execution), effectively resolving the contradiction between security and speed.
2Reliability
If more internal states and rounds are used, then cryptographic security is enhanced, but processing speed decreases
Solution Approach 1:
The patent divides the internal state processing into multiple parallel segments, where each segment processes a portion of the data independently. This segmentation allows the system to maintain a large effective state space for security while processing multiple segments simultaneously, thereby preserving cryptographic security without sacrificing processing speed.
Solution Approach 2:
The patent merges the outputs of multiple parallel processing paths to produce the final hash output. By combining results from several concurrent processing streams, the system achieves both high processing speed (through parallel execution) and strong cryptographic security (through the combined complexity of all processing paths).
Data Source
AI summary
A hashing circuit includes gates or combinations of gates, each being configured to asynchronously output a state value in response to a respective input to the gate or combination of gates. Each of a plurality of bit inputs is asynchronously coupled to one or more of the inputs to the gates or combinations of gates, and each of one or more of the outputted state values is asynchronously coupled to one or more inputs of other gates or combinations of gates, in combination with one or more of the bit inputs and/or one or more other outputted state values. All or some of the state values, or output bits from a logical function of all or some of the state values, or a combination of a first subset of the state values and a logical function of a second subset of state values, are provided as hash-circuit output bits.