Round-Interleaved Ciphering Circuit for Side Channel Attack Resistance

The patent divides the cryptographic computation into multiple processing rounds that are executed in an interleaved sequence. By segmenting the computation timeline and alternating between rounds of different cryptographic operations, the system reduces signal leakage patterns that would otherwise expose side channel information, thereby improving security without requiring additional protective circuitry

The patent implements dynamic interleaving of processing rounds where the execution sequence is adjusted based on the specific cryptographic operations being performed. This dynamic scheduling approach allows the system to adapt the timing and sequence of operations to minimize signal leakage while maintaining computational efficiency, resolving the contradiction between security and performance

The patent performs preliminary interleaving of processing rounds before the actual cryptographic computation begins. By pre-scheduling the sequence of operations and preparing the interleaved execution plan in advance, the system ensures that security measures are built into the computation structure itself, avoiding performance penalties that would arise from adding protective layers during execution

The patent maintains continuous execution of cryptographic operations through interleaved processing rounds. Instead of completing one entire cryptographic operation before starting another, the system continuously executes multiple rounds in parallel, ensuring that useful computational action never stops while distributing the workload to prevent signal leakage patterns