Rounded Device Isolation Layer for Precise Trench Patterning

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Solution Overview

Problem

The increasing complexity of semiconductor device manufacturing processes, particularly in forming conductive patterns and insulating patterns, is exacerbated by the need for more compact and integrated semiconductor devices, leading to challenges in achieving precise and efficient device isolation.

Innovation Solution

A method involving thermal oxidation and atomic layer deposition processes to form a device isolation layer with a round top surface, followed by dry etching to expose the substrate, ensuring precise patterning of high-k dielectric and conductive material layers, thereby enhancing the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional manufacturing processes are used to form device isolation layers, then the manufacturing process is simpler, but the top surface of the device isolation layer becomes irregular and generates unwanted residue

Engineering Contradiction:
Improvetop surface uniformity of device isolation layerVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The device isolation layer formation is divided into multiple sequential steps: forming a trench, conformally forming a first insulating layer, forming a second insulating layer, and performing dry etching. This segmentation allows each step to be optimized independently, achieving a uniform round top surface while maintaining process control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The trench is formed in advance before forming the insulating layers. This preliminary action creates a defined space that guides the subsequent conformal deposition processes, ensuring that the insulating layers are formed precisely where needed and contributing to the final uniform top surface

Inventive Principle:
Principle #10Preliminary action

2Productivity

If design rules are decreased to achieve higher integration, then device compactness is improved, but the difficulty of forming precise conductive and insulating patterns increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidpatterning precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs specific process parameters including thermal oxidation for conformal deposition, atomic layer deposition for precise thickness control, and dry etching for clean pattern definition. These parameter changes enable precise patterning at reduced design rules by controlling deposition and etching rates to achieve the required dimensional accuracy

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Conventional mechanical or chemical-mechanical polishing methods are replaced with a combination of thermal oxidation and atomic layer deposition followed by dry etching. This substitution provides better control over film thickness and pattern definition, achieving the precision needed for reduced design rules without relying on mechanical processes that may compromise pattern fidelity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the formation of semiconductor devices with improved device isolation layers, reducing unwanted residue and enabling efficient integration of conductive materials, thus facilitating the production of compact and high-performance semiconductor devices.

Implementation Method 1

conformally forming a first insulating layer on a top surface of the substrate and on an inner wall of the trench through a thermal oxidation process

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Implementation Method 2

forming a second insulating layer on the first insulating layer through an atomic layer deposition process

Methodology Applied
Scientific EffectAtomic layer deposition: Deposition (physical)

Implementation Method 3

performing a dry etching process on the second insulating layer and the first insulating layer such as to expose the top surface of the substrate

Methodology Applied
Scientific EffectDry etching: Plasma

Data Source

PatentUS20250218862A1Method of manufacturing device isolation layer and method of manufacturing semiconductor device by using the same
Publication Date: 2025.07.03 SAMSUNG ELECTRONICS CO LTD
  • US20250218862A1 patent drawing
  • US20250218862A1 patent drawing
  • US20250218862A1 patent drawing

AI summary

A method incudes forming a trench in a substrate; conformally forming a first insulating layer on a top surface of the substrate and on an inner wall of the trench through a thermal oxidation process; forming a second insulating layer on the first insulating layer through an atomic layer deposition process such that a portion of the second insulating layer is within the trench; performing a dry etching process on the second insulating layer and the first insulating layer such as to expose the top surface of the substrate; and forming a device isolation layer inside the trench, the device isolation layer including a first insulating pattern formed by etching the first insulating layer and a second insulating pattern formed by etching the second insulating layer, wherein the device isolation layer has a round top surface.