Rounded Metal Plug for Semiconductor Interconnect Alignment

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Solution Overview

Problem

The complexity of semiconductor device manufacturing leads to misalignment issues in interconnect structures, affecting the performance and reliability of these devices.

Innovation Solution

A semiconductor device design featuring a first metal plug with a rounded top surface and a second metal plug in direct contact with its sidewall, along with an etch stop layer and dielectric layers, which increases contact area and evenly distributes electric field strength, thereby improving performance and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional manufacturing processes are used for semiconductor devices, then manufacturing complexity increases, but misalignment in interconnect structures occurs

Engineering Contradiction:
Improvealignment precisionVSAvoidmanufacturing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The first metal plug is formed with a rounded top surface instead of a flat surface. This curvature allows the second metal plug to make contact at multiple points around the rounded surface, creating a tolerance zone that accommodates manufacturing misalignment while maintaining reliable electrical connection

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The rounded top surface of the first metal plug serves as a pre-designed compensation mechanism that cushions against potential misalignment issues before they occur during assembly. The curved geometry provides a built-in margin of error that prevents complete connection failure even when alignment is imperfect

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11605557B2Method for preparing semiconductor device with metal plug having rounded top surface
Publication Date: 2023.03.14 NAN YA TECH
  • US11605557B2 patent drawing
  • US11605557B2 patent drawing
  • US11605557B2 patent drawing

AI summary

A for preparing a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, and forming an etch stop layer over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer, and forming a first metal plug penetrating through the second dielectric layer, the etch stop layer and the first dielectric layer. The first metal plug protrudes from the second dielectric layer. The method further includes performing an anisotropic etching process to partially remove the first metal plug such that the first metal plug has a convex top surface, and forming a third dielectric layer covering the second dielectric layer and the convex top surface of the first metal plug. In addition, the method includes forming a second metal plug over the first metal plug.