Rounded Nanowire Transistor Structure for Gate Fill and Leakage Control
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Solution Overview
Problem
Nanowire transistors face challenges such as sharp corners causing poor gate-metal fill, increased electric fields, charge accumulation, current leakage, and inconsistent performance due to irregular geometry and residual germanium impurities, which hinder device scaling and reliability.
Innovation Solution
Employing controlled isotropic dry and wet etching, oxidation, and annealing processes to shape nanowires, resulting in rounded cross-sections with reduced surface roughness and minimal residual germanium, improving the nanowire interface for better gate dielectric and metal gate deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If nanowires are released using conventional etching processes, then the nanowire channel region can be formed, but sharp corners and irregular geometry are created causing poor gate-metal fill and increased electric fields
Solution Approach 1:
The patent applies curvature by transforming the nanowire cross-section from sharp-cornered rectangular shapes to rounded shapes with radii of curvature of 5-20 nm. This is achieved through controlled isotropic etching processes that preferentially remove material from high-curvature regions (sharp corners), resulting in uniformly rounded nanowire cross-sections that improve gate-metal fill and reduce electric field concentration
Solution Approach 2:
The patent changes the etching parameters by using isotropic etchants (such as XeF2, CF4, or SF6) with specific etch rates and exposure times to control the rounding process. By adjusting etch temperature, pressure, and duration, the nanowire cross-sectional shape is transformed from rectangular to circular with controlled radius, optimizing both fabrication quality and device performance
2Quantity of substance
If conventional release processes are used, then nanowires can be freed from sacrificial layers, but residual germanium impurities remain causing charge accumulation and current leakage
Solution Approach 1:
The patent extracts residual germanium impurities from the nanowire structure by employing selective etching processes. The isotropic etchants used preferentially remove germanium material while preserving the silicon nanowire core, thereby eliminating charge accumulation centers and improving carrier mobility and device reliability
Solution Approach 2:
The patent converts the potentially harmful residual germanium into a beneficial process feature by using germanium's higher etch rate with isotropic etchants as a selective removal mechanism. The residual germanium from sacrificial layer release becomes a target for subsequent cleaning steps, where its preferential etching eliminates impurities without damaging the silicon nanowire
3Ease of manufacture
If sharp-cornered nanowires are used, then fabrication is simpler, but electric fields concentrate at corners causing poor gate-metal fill and increased leakage
Solution Approach 1:
The patent applies curvature to eliminate sharp corners by rounding the nanowire cross-section. This geometric transformation distributes electric fields uniformly across the nanowire surface, preventing field concentration at corners and improving gate-metal deposition quality while maintaining fabrication efficiency through controlled isotropic etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances transistor mobility and reliability by reducing sharp corners, minimizing germanium impurities, and achieving consistent device performance across nanowires, allowing further scaling and improved performance.
Implementation Method 1
controlled isotropic dry and wet etching
Implementation Method 2
oxidation, and annealing processes
Implementation Method 3
oxidation, and annealing processes
Data Source
AI summary
A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.