Rounded Nanowire Transistor Structure for Clean Gate Interfaces
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Solution Overview
Problem
Nanowire transistors face challenges due to sharp corners causing poor gate-metal fill, increased electric fields, and reduced reliability, as well as residual germanium impurities and irregular geometry leading to inconsistent performance.
Innovation Solution
The use of controlled isotropic dry and wet etching, oxidation, and annealing processes to shape nanowires into rounded forms with minimal surface roughness, removing residual materials and improving the interface before gate dielectric deposition, thereby enhancing transistor mobility and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nanowires are formed with sharp corners through conventional fabrication, then manufacturing is simpler, but gate-metal fill is poor and electric fields increase reducing reliability
Solution Approach 1:
The patent applies preliminary action by performing etch-back and oxidation processes on the nanowires before gate dielectric deposition. This pre-shaping of nanowires with rounded corners at an earlier stage prevents the harmful effects of sharp corners during subsequent gate-metal filling and operation, thereby improving reliability without compromising manufacturing feasibility
Solution Approach 2:
The patent implements spheroidality by intentionally rounding the corners of nanowires through controlled etch-back and oxidation processes. This curvature transformation eliminates sharp corners that cause poor gate-metal fill and excessive electric fields, directly improving transistor reliability and performance
2Manufacturing precision
If nanowires retain residual germanium impurities from fabrication, then manufacturing process is simpler, but device performance becomes inconsistent
Solution Approach 1:
The patent applies preliminary action by performing multiple cleaning cycles including etch-back and oxidation processes before gate dielectric deposition. This pre-cleaning removes residual germanium impurities at an earlier stage, ensuring consistent device performance without adding excessive complexity to the overall manufacturing process
Solution Approach 2:
The patent implements parameter changes by controlling the oxidation process parameters to selectively remove germanium impurities while preserving the silicon nanowire structure. By adjusting oxidation conditions, the process achieves effective impurity removal and consistent device performance
3Manufacturing precision
If nanowires have irregular geometry, then fabrication is simpler, but carrier mobility decreases and performance varies
Solution Approach 1:
The patent applies preliminary action by performing etch-back processing to uniformize nanowire geometry before gate dielectric deposition. This pre-shaping ensures consistent nanowire dimensions and smooth surfaces, leading to improved carrier mobility and consistent device performance
Solution Approach 2:
The patent implements parameter changes by controlling etch-back process parameters to achieve uniform nanowire geometry. By adjusting etch conditions, the process removes material consistently across all nanowires, producing uniform dimensions and smooth surfaces that enhance carrier mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the geometry and cleanliness of nanowires, reducing surface roughness and impurities, leading to increased carrier mobility, higher operating voltage, and consistent device performance.
Implementation Method 1
controlled isotropic dry and wet etching
Implementation Method 2
oxidation, and annealing processes
Implementation Method 3
oxidation, and annealing processes
Data Source
AI summary
A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.