Rounded Semiconductor Pattern Layout for eHV Electric Field Relief

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Solution Overview

Problem

Embedded high-voltage (eHV) semiconductor devices face reliability issues due to extremely high electric fields at pointed features, which can lead to dielectric burn-out, caused by higher charge density and voltage requirements compared to ordinary logic devices.

Innovation Solution

A semiconductor pattern with a rounding feature is formed using an optical proximity correction (OPC) tool, where the line width gradually increases to a maximum and then decreases to create a rounding feature at the end, reducing the electric field by increasing the radius of curvature.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If pointed features are used in semiconductor pattern, then manufacturing precision is improved, but electric field concentration increases causing dielectric burn-out

Engineering Contradiction:
Improvepattern precisionVSAvoidelectric field concentration
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies curvature by replacing pointed features with rounded features having a radius of curvature R. This spheroidality principle directly addresses the electric field concentration problem by eliminating sharp corners where charge density accumulates, thereby preventing dielectric burn-out while maintaining manufacturing precision through controlled rounding parameters

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Object-affected harmful factors

If rounding feature with larger width is formed, then electric field is reduced, but line width variation increases

Engineering Contradiction:
Improveelectric fieldVSAvoidline width control
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies local quality by implementing rounding features only at specific locations (line ends or corners) rather than uniformly across the entire pattern. The rounding radius R is carefully controlled to be within a specific range (0.05W to 0.5W, where W is the original line width), ensuring that the electric field is reduced at critical points while maintaining overall line width control and pattern integrity

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240266286A1Semiconductor pattern and method of rounding the same
Publication Date: 2024.08.08 UNITED MICROELECTRONICS CORP
  • US20240266286A1 patent drawing

AI summary

A semiconductor pattern is provided in the present invention, including a first line extending to one end in a first direction and a second line extending in a second direction perpendicular to the first direction and adjacent to the end of the first line in the first direction, wherein the end of the first line is provided with a rounding feature, the first line has a width in the second direction, and the width is gradually increased to a maximum width toward the end and gradually converged to form the rounding feature.