Rounded Transistor Gates via Double-Exposure Lithography
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Solution Overview
Problem
Conventional non-volatile memory cells face electron discharge issues due to thin insulating layers around transistor gates, leading to retention problems and increased manufacturing costs and inefficiencies when attempting to thin nitrided silicon oxide films using specialized etching tools.
Innovation Solution
The transistor gates are fabricated with rounded edges and corners to allow thicker insulating material deposition, reducing backend leakage current and enhancing electron retention, using a double-exposure photolithography technique compatible with standard CMOS processes without the need for dedicated equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the nitrided silicon oxide film is thinned by selective etching, then electron discharge is reduced, but manufacturing cost and complexity increase due to specialized equipment requirements
Solution Approach 1:
The gate electrode edges and corners are rounded with a radius of curvature between 5-50 nm, which prevents the formation of thin spots in the insulating film during deposition. This curvature ensures uniform film thickness throughout the structure, eliminating the need for selective etching of the nitrided silicon oxide film while maintaining reliable electron retention in non-volatile memory cells.
Solution Approach 2:
The gate electrode edges are rounded during the gate formation process itself, before the insulating film is deposited. This preliminary shaping action ensures that the subsequently deposited insulating film maintains uniform thickness without requiring post-deposition etching operations, thereby simplifying the manufacturing process while achieving the desired electron retention reliability.
2Reliability
If selective etching of nitrided silicon oxide film is performed, then electron discharge is reduced, but manufacturing time and productivity decrease due to additional process steps
Solution Approach 1:
By rounding the gate electrode edges and corners during fabrication, the patent eliminates the need for subsequent selective etching steps of the nitrided silicon oxide film. This curvature-based approach ensures uniform insulating film thickness from the outset, thereby maintaining high manufacturing productivity while achieving reliable electron retention without time-consuming additional process steps.
Solution Approach 2:
The gate electrode shaping is performed as a preliminary action during the standard CMOS fabrication process, before any insulating film deposition occurs. This upfront preparation eliminates the need for later selective etching operations, thereby maintaining manufacturing efficiency and productivity while ensuring reliable electron retention through uniform film thickness.
3Ease of manufacture
If standard CMOS processes are used without gate rounding, then manufacturing is simpler, but electron discharge increases due to thin insulating film at edges and corners
Solution Approach 1:
The patent incorporates gate electrode rounding with a radius of curvature between 5-50 nm into the standard CMOS fabrication process. This curvature prevents the formation of thin spots in the insulating film at edges and corners, thereby maintaining electron retention reliability while preserving the simplicity and compatibility of standard CMOS manufacturing processes.
Solution Approach 2:
The patent modifies a key geometric parameter of the gate electrode (edge radius of curvature) from sharp corners to rounded edges with a specific curvature radius. This parameter change ensures uniform insulating film thickness during deposition, thereby maintaining both the ease of manufacture through standard CMOS processes and the reliability of electron retention without requiring specialized equipment or complex additional steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves electron retention in non-volatile memory cells by reducing leakage current and maintaining manufacturing efficiency and cost-effectiveness by adhering to standard CMOS processes.
Implementation Method 1
a first portion of the photoresist material is exposed to light at a first focal distance from the lens to a first depth within the photoresist material, causing a first chemical change in the first portion of the photoresist material
Implementation Method 2
a second portion of the photoresist material is exposed to light at a second focal distance from the lens to a second depth within the photoresist material, causing a second chemical change in the second portion of the photoresist material
Data Source
AI summary
A method for forming a transistor gate includes performing a first exposure of a photo-resist material on a semiconductor device. The first exposure defines a line pattern in the photo-resist material. The method also includes performing a second exposure of the photo-resist material, where the second exposure trims a resist profile of the line pattern. The method further includes etching a conductive material on the semiconductor device to form a transistor gate based on the line pattern. The first exposure could represent a best focus exposure of the photo-resist material, and the second exposure could represent a positive focus exposure of the photo-resist material. The trimming of the line pattern's resist profile may cause the transistor gate to have at least one of a rounded edge and a rounded corner. This may allow a thicker insulating material, such as tetraethylorthosilicate, to be deposited around portions of the transistor gate.