Route Aggregation Tree Structure for Network Loop Prevention
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Solution Overview
Problem
Existing route aggregation methods in communications networks fail to automatically aggregate multiple routes and prevent routing loops across multiple network elements, leading to inefficient data routing and potential loops.
Innovation Solution
A distributed network switch with a route aggregation module that uses a tree data structure to store route descriptors, where each route descriptor includes a next hop destination and indicators for route aggregation, allowing for automatic aggregation of host routes and prevention of routing loops by selecting the best next hop destination based on the number of routes covered.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If manual route aggregation is used, then route aggregation can be achieved, but automatic aggregation across multiple network elements cannot be provided
Solution Approach 1:
The patent segments the route aggregation process into distributed components at different network elements (aggregate routes module at core network element, route selection module at access network element). Each component handles a specific portion of the aggregation task independently, enabling automatic coordination across multiple network elements without requiring a single complex centralized system.
Solution Approach 2:
The patent implements feedback mechanisms where access network elements send route information to core network elements, which then generate aggregate routes and send back control information. This feedback loop enables automatic coordination and adjustment of routing decisions across the network, allowing the system to adapt to changing network conditions dynamically.
2Reliability
If route aggregation is performed without coordination, then simpler processing is achieved, but routing loops cannot be prevented
Solution Approach 1:
The patent introduces core network elements as intermediaries between access network elements. These core elements act as mediators that receive route information from access elements, process it through the aggregate routes module, and generate coordinated aggregate routes. This intermediary layer enables routing loop prevention by centralizing the decision-making logic while maintaining distributed operation.
Solution Approach 2:
The patent performs preliminary actions by having access network elements send their route information to core network elements before final routing decisions are made. The aggregate routes module processes this information in advance to determine optimal aggregate routes, ensuring that routing decisions are made with full knowledge of the network topology and potential loop conditions before data forwarding occurs.
3Quantity of substance
If multiple host routes are maintained, then routing flexibility is improved, but memory usage in access switches increases
Solution Approach 1:
The patent merges multiple host routes into aggregate routes at core network elements. Instead of maintaining separate routing entries for each host route in access switches, the system creates aggregated routing entries that represent multiple hosts simultaneously. This merging reduces the number of individual route entries that need to be stored and processed, thereby reducing memory usage while maintaining routing flexibility through the aggregate route structure.
Solution Approach 2:
The patent transitions from a flat routing table structure to a hierarchical tree structure for organizing routes. The tree structure allows routes to be organized by common prefixes, enabling efficient aggregation and reducing the dimensional complexity of route storage. This hierarchical organization enables access switches to use more compact routing information while maintaining the ability to reach multiple destinations.
Data Source
AI summary
An apparatus includes a memory configured to store multiple route descriptors as a tree, a communications interface configured to be in communication with an access switch, and a processor operatively coupled to the memory and the communications interface. Each route descriptor is a node within the tree, and includes a next hop destination associated with a next hop destination of a route associated with that route descriptor and a next hop indicator associated with a quantity of routes represented by that route descriptor. A first route descriptor has a first child route descriptor and a second child route descriptor. The processor is configured to define, at a first time, a value of the next hop destination of the first route descriptor and to send, at a second time after the first time, the value of the next hop destination of the first route descriptor to the access switch.