Route Update System Bypasses Control Plane Bottlenecks

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Solution Overview

Problem

Existing network routing systems face significant delays and inefficiencies in updating routing tables due to control plane bottlenecks, particularly with the implementation of Network Function Virtualization (NFV), which limits the frequency and speed of dynamic route changes, impacting the performance of Software Defined Networking (SDN) and NFV adoption.

Innovation Solution

The Route Update System (RUS) bypasses control plane update bottlenecks by transferring update instructions directly from a control plane to a data plane, using an Update Snoop Module (USM) and Update Inject Module (UIM) to manage routing table updates efficiently, allowing for atomic updates and high-frequency changes without interrupting other processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If routing table updates are performed through the control plane, then routing updates can be made, but update speed is limited to thousands per second due to control plane bottlenecks

Engineering Contradiction:
Improverouting table update speedVSAvoidcontrol plane bottleneck
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the routing update function by separating the control plane (CPU) from the data plane (routing table memory access). The USM/CPU handles update generation while the UIM/memory interface handles high-speed update execution, allowing independent optimization of each component and achieving millions of updates per second through parallel processing paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary components (USM and UIM) that bridge the control plane and data plane. The USM intercepts update requests from the CPU and the UIM delivers them to the routing table memory, creating a dedicated high-speed pathway that bypasses control plane limitations while maintaining system coherence through arbitration mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If high-frequency routing updates are implemented, then routing efficiency improves, but conflicts with other memory access processes occur

Engineering Contradiction:
Improverouting update frequencyVSAvoidmemory access conflict
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic arbitration that adapts to real-time memory access conditions. The UIM works with the memory interface to dynamically allocate bandwidth and prioritize routing updates when the routing table needs modification, while yielding to other critical memory accesses when necessary, ensuring both high productivity and system reliability through flexible resource management.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent incorporates feedback mechanisms where the UIM monitors memory access status and routing update requirements, adjusting its operation accordingly. When the routing table requires updates, the system activates high-priority pathways; when other processes dominate memory access, the system scales back update frequency, maintaining reliability while maximizing overall productivity through continuous adaptation.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10506434B2System for accelerated network route update through exclusive access to routing tables
Publication Date: 2019.12.10 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US10506434B2 patent drawing
  • US10506434B2 patent drawing
  • US10506434B2 patent drawing

AI summary

A route update system (RUS) may support increased efficiency and speed for performing a routing table update. The RUS may include a control plane processor device, which may implement update snoop module circuitry. The RUS may also include a data routing switch, which may implement update inject module circuitry. The RUS may include one or more RUS connectivity systems that link the update snoop module circuitry and the update inject module circuitry.