Router Buffer Allocation for Mixed-Width Bus Systems
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Solution Overview
Problem
Conventional techniques for improving buffer efficiency in semiconductor integrated circuits, which connect bus masters with different bus widths and protocols, are not effective as they require packet loss, which is not permissible in these systems, leading to inefficient use of router buffers and limitations in recycling bus masters.
Innovation Solution
A bus system with bus interface apparatuses that include reception buffers, size information storage, header information generators, packetizers, and transmission controllers, and routers with packet analyzers, buffer storage controllers, and output controllers that use size information to efficiently allocate buffer space and manage packet transmission based on bus width, ensuring no packet loss and efficient buffer use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional buffer management techniques are applied to semiconductor bus systems, then buffer space can be allocated dynamically, but packet loss occurs which is not permissible in these systems
Solution Approach 1:
The patent applies preliminary action by pre-allocating buffer spaces according to bus width categories before packets arrive. The router controller divides the buffer into multiple regions corresponding to different bus widths (e.g., 8-bit, 16-bit, 32-bit regions), ensuring that buffer spaces are ready in advance for packets of various sizes without causing packet loss.
2Reliability
If buffer space is increased to prevent packet loss, then reliability improves, but chip area and power consumption increase
Solution Approach 1:
The patent applies local quality by allocating different buffer space sizes to different bus width categories based on their actual needs. Instead of providing uniform large buffer space for all packets, the system allocates smaller buffer regions for narrow bus widths (e.g., 8-bit) and larger regions for wide bus widths (e.g., 32-bit), optimizing chip area usage while preventing packet loss for each category.
3Adaptability or versatility
If various bus masters with different bus widths are connected together, then adaptability improves, but buffer management complexity increases
Solution Approach 1:
The patent applies parameter changes by using bus width as the key parameter for buffer management. The router controller identifies the bus width of incoming packets and automatically directs them to the corresponding pre-defined buffer region. This parameter-based approach simplifies buffer management complexity while maintaining compatibility with various bus masters of different widths.
Data Source
AI summary
In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.