Router Floating Buffer Architecture for Single-Cycle Path Selection
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Solution Overview
Problem
Current router architectures face inefficiencies in packet routing, particularly in transferring packets between ingress and egress ports, leading to high latency and limited throughput due to the discrete nature of computer systems and routers, which can be exacerbated in integrated circuit environments.
Innovation Solution
The implementation of a router architecture that utilizes floating buffers and multiplexers to dynamically allocate and release buffer identifiers, allowing for concurrent packet transfers between ingress and egress ports, enabling multiple routes in a single clock cycle and reducing latency through dual-port memory structures for overlapping write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional router architectures are used with discrete components, then the router can transfer packets between ingress and egress ports, but the latency is high and throughput is limited
Solution Approach 1:
The patent combines the router control logic and packet buffering functions into a unified architecture where the controller directly manages floating buffers that are shared between multiple ingress and egress ports. This integration eliminates intermediate processing stages and reduces the number of discrete components, enabling faster packet transfer while maintaining high throughput through efficient resource utilization.
2Productivity
If multiple packets are transferred concurrently through discrete router components, then throughput can be increased, but the complexity of managing multiple paths and buffers increases
Solution Approach 1:
The floating buffers are designed to be universally accessible by multiple ingress and egress ports, serving as shared resources rather than dedicated buffers for specific port pairs. The controller dynamically allocates and manages these floating buffers based on current routing needs, enabling multiple concurrent packet transfers while simplifying the overall buffer management architecture through centralized control.
3Productivity
If dedicated buffers are allocated for each ingress-egress port pair, then packet routing is simplified, but the router throughput is limited by the fixed buffer allocation
Solution Approach 1:
The patent implements dynamic buffer allocation where floating buffers can be dynamically assigned to different ingress-egress port pairs based on real-time routing requirements. The controller continuously monitors and reconfigures buffer assignments, allowing the system to adapt to varying traffic patterns and maximize throughput while maintaining the flexibility to handle diverse routing scenarios.
Data Source
AI summary
Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.