Router Microprocessor Direct PCIe Lane Segmentation
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Solution Overview
Problem
Software-based routers are limited by CPU bandwidth, memory, and processing capacity, leading to reduced network performance compared to hardware-based routers, and they often share PCIe bandwidth when using multiple IO interfaces, resulting in reduced maximum bandwidth for each interface.
Innovation Solution
A router design that includes a microprocessor communicating with a Southbridge or platform controller hub, utilizing multi-lane PCI graphics ports to facilitate independent signal transfer between the microprocessor and IO ports, allowing for bifurcation or trifurcation of these ports to provide multiple single-lane PCI communication paths, and incorporating a PCI switch to support automatic fall-back of PCI lanes, enabling efficient communication paths independent of the Southbridge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based routers use standard CPU instructions and memory to process network packets, then flexibility and adaptability are improved, but processing speed and network performance deteriorate due to sequential processing and multiple data movement steps
Solution Approach 1:
The patent segments the PCIe bandwidth into multiple independent lanes (e.g., x16 split into four x4 lanes) that can be independently allocated to different I/O interfaces. This segmentation allows parallel data transmission paths, enabling software-based routers to achieve higher throughput by eliminating the bottleneck of shared PCIe bandwidth while maintaining the flexibility of software-based packet processing.
2Device complexity
If multiple I/O interfaces are connected through a Southbridge or platform controller hub, then device complexity is reduced, but PCIe bandwidth is shared resulting in reduced maximum bandwidth for each interface
Solution Approach 1:
The patent extracts the high-speed PCIe communication path from the traditional Southbridge-based architecture by establishing direct communication between the CPU and I/O interfaces through dedicated PCIe lanes. This extraction eliminates the bandwidth-sharing bottleneck of the Southbridge while maintaining architectural simplicity, as the CPU directly manages multiple PCIe lanes without requiring additional hub components.
3Productivity
If hardware-based routers use pre-wired logic gate structures, then processing speed and latency are improved, but adaptability and ease of upgrading routing protocols deteriorate
Solution Approach 1:
The patent changes the operational parameters of the CPU by dedicating specific PCIe lanes directly to the CPU core, enabling the processor to handle network packets at speeds approaching hardware-based router performance. This parameter change allows the software-based router to achieve high-speed processing while retaining the ability to dynamically upgrade routing protocols through software updates, effectively bridging the performance gap between hardware and software implementations.
Data Source
AI summary
A router for routing signals on communications networks; said router comprising a plurality of I/O ports for input to the router of said signals and for output from the router of said signals; said router comprising at least one microprocessor; said router adapted such that said microprocessor communicates with at least one of said I/O ports independently of any Southbridge or platform controller hub (SPCH) associated with said microprocessor.