Routerless Networks-on-Chip Using Wire Loops
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Solution Overview
Problem
Conventional networks-on-chip (NoCs) for chip multiprocessors face challenges in scalability and efficiency due to high power consumption and area requirements, particularly because of the use of routers, which limit the utilization of available wiring resources and result in increased latency and hop counts.
Innovation Solution
A routerless NoC design utilizing wire-based circular paths to interconnect cores, employing a recursive algorithm to generate deterministic circular paths that eliminate the need for routers, and implementing low-area-cost network interfaces with shared buffers to reduce power and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If routers are used to interconnect cores in an NoC, then connectivity and routing control are improved, but power consumption and area requirements increase significantly
Solution Approach 1:
The patent removes routers from the NoC architecture entirely, extracting the routing function from dedicated router components and implementing it through wire-based circular paths. This eliminates the power-consuming router hardware while maintaining core interconnectivity through simplified wiring structures.
Solution Approach 2:
The patent makes wiring resources universal by enabling them to perform both interconnection and routing functions simultaneously. The circular wire paths serve multiple purposes: connecting cores, providing routing control, and enabling communication without requiring separate router components, thus reducing overall power consumption.
2Reliability
If routers are used to interconnect cores in an NoC, then routing control is improved, but area requirements increase
Solution Approach 1:
The patent extracts the routing control function from physical router components and implements it through logical wire-based circular paths. This eliminates the area-consuming router hardware while preserving routing capability through the wiring topology itself.
Solution Approach 2:
The patent merges routing control functionality with the interconnection wiring structure. The circular wire paths simultaneously serve as both the physical connection medium and the routing control mechanism, eliminating the need for separate router components and reducing overall area.
3Reliability
If conventional router-based NoC designs are used, then connectivity is maintained, but wiring resource utilization is poor and latency increases
Solution Approach 1:
The patent pre-establishes circular wire paths during the design phase that provide predetermined routing routes between all core pairs. This preliminary structuring of communication paths eliminates the need for dynamic routing decisions at runtime, reducing latency by avoiding the time-consuming router switching processes.
Data Source
AI summary
The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip (“NoCs”), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a “multi-core processor”). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.