Routing-Aware Placement for Electronic Design
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Solution Overview
Problem
Conventional electronic design floorplanners and placement tools fail to account for routing requirements, leading to routability issues due to insufficient consideration of neighboring layers, resulting in the need for double vias which increase costs and complexity, especially in advanced technology nodes.
Innovation Solution
Implementing routing-aware placement techniques that identify optimal block locations based on pin access points and via locations across multiple layers, using candidate location filtering and cost estimation to maximize pin access and minimize routing challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional floorplanner or placement tools are used, then placement can be completed according to design rules, but routing issues occur due to insufficient consideration of neighboring layers
Solution Approach 1:
The patent applies preliminary action by performing routing-aware placement during the placement stage, before routing is executed. The placement tool pre-identifies optimal via locations and pin access points on neighboring layers, and uses this information to guide block placement decisions, thereby preventing routing issues before they occur
Solution Approach 2:
The patent implements feedback by having the placement tool query routing information from neighboring layers during placement, and using this routing feedback to adjust placement decisions. The system continuously monitors pin access quality and via placement feasibility, feeding this information back into the placement optimization process
2Reliability
If double vias are used to resolve routing issues, then routing reliability improves, but implementation cost and silicon real estate increase
Solution Approach 1:
The patent prevents the need for double vias by performing preliminary routing-aware placement that ensures single via feasibility from the outset. By pre-identifying optimal pin locations and via access points during placement, the system eliminates routing failures before they occur, making double vias unnecessary
Solution Approach 2:
The patent replaces expensive and complex double via solutions with simpler, more cost-effective single via implementations. By optimizing placement to ensure adequate pin coverage of routing tracks, the system achieves reliable routing with minimal via structures, reducing both implementation cost and silicon real estate consumption
3Adaptability or versatility
If blocks are placed without considering routing tracks, then placement flexibility is maintained, but pin access to routing tracks becomes insufficient
Solution Approach 1:
The patent changes the optimization parameters of the placement tool to include routing-aware metrics. Instead of only considering design rules and congestion, the system incorporates pin access quality, via placement feasibility, and routing track alignment as optimization parameters, thereby achieving both flexibility and precision
Solution Approach 2:
The system performs preliminary analysis of routing track locations and pin access requirements before finalizing block placement. By pre-identifying optimal pin locations and their correspondence to routing tracks, the system ensures manufacturing precision while maintaining placement flexibility through iterative optimization
Data Source
AI summary
Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.