Routing-Aware Placement for Electronic Design Floorplanning
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Solution Overview
Problem
Conventional electronic design floorplanning tools lack awareness of routing requirements, leading to inefficiencies and errors during the routing stage, particularly with advanced technology nodes where single-layer routing directionality causes routability issues, and fail to account for neighboring layers, resulting in suboptimal placement and increased computational resources.
Innovation Solution
Implementing a routing-aware placement method that dynamically tiles free design space into spacetiles, constructs switchbox routing problems, and generates geometric routes on the fly to ensure compliance with design rules and constraints, including those of neighboring layers, thereby optimizing the placement layout for routability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floorplanning tools are used, then placement can be performed according to basic design rules, but routing awareness is lacking leading to errors and rework during routing stage
Solution Approach 1:
The patent applies preliminary action by performing routing-aware placement during the floorplanning stage before the actual routing occurs. The system proactively considers routing requirements, track patterns, and congestion information when placing blocks, thereby preventing routing violations and reducing rework needs while maintaining placement efficiency through automated routing-aware optimization
Solution Approach 2:
The system implements feedback mechanisms by using routing information, track pattern data, and congestion estimates from the routing stage to feed back into the placement optimization. This iterative feedback loop allows the placement to be continuously refined based on actual routing constraints and requirements, ensuring high routing compliance without sacrificing placement productivity
2Reliability
If routing requirements are considered during placement, then routability is improved, but computational complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the complex routing-aware placement problem into manageable sub-problems. The design space is segmented into regions with different routing characteristics, and the placement optimization is performed locally in these segments rather than globally, reducing overall computational complexity while maintaining high routability through localized routing-aware decisions
Solution Approach 2:
The system utilizes parameter changes by dynamically adjusting placement criteria and optimization parameters based on routing requirements. The system changes placement parameters such as block positioning, orientation, and spacing based on track pattern information and congestion estimates, thereby improving routability through parameter optimization without requiring excessive computational resources
3Ease of manufacture
If single-layer routing directionality is enforced, then manufacturing simplicity is improved, but routability issues arise at advanced technology nodes
Solution Approach 1:
The patent applies dimensionality change by considering routing requirements across multiple dimensions and layers rather than being constrained to a single layer and direction. The system evaluates track patterns and routing possibilities in three-dimensional space, allowing placement decisions that account for vertical routing paths and multi-layer connectivity, thereby maintaining manufacturability while improving routability at advanced nodes
4Reliability
If placement is optimized for routability, then routing success is improved, but placement time increases
Solution Approach 1:
The system applies preliminary action by pre-computing routing information, track patterns, and congestion estimates during the placement stage itself rather than waiting for the routing stage. This proactive approach allows placement to be optimized for routing success from the beginning, reducing the need for time-consuming rework and iterations later in the design flow
Solution Approach 2:
The patent applies partial action by performing routing-aware optimization to the extent necessary to ensure routability without over-engineering the placement process. The system uses heuristics and estimates to achieve sufficient routing awareness without the full computational burden of complete routing analysis, thereby balancing routing success with placement time efficiency
Data Source
AI summary
Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the floorplan or placement layout with one or more geometric routes based in part or in whole upon the legal location.