Global Routing Channels Over Active Regions
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Solution Overview
Problem
Global routing channels in application-specific integrated circuits (ASICs) decrease the fill ratio of standard cells, leading to increased chip sizes, higher costs, and lower circuit speeds due to occupied chip real estate.
Innovation Solution
The arrangement of standard CMOS integrated circuit cells with global routing channels routed over PMOS active regions, allowing for side-by-side placement of cells to maximize fill ratio while maintaining global connectivity by positioning VDD and ground power rails between the global routing channels and the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If global routing channels are introduced to improve routing feasibility, then routing connectivity is improved, but fill ratio of standard cells decreases
Solution Approach 1:
The patent routes global routing channels over the active regions of standard cells (specifically over PMOS active regions) rather than between cells in the traditional horizontal/vertical corridors. This spatial reconfiguration allows routing channels to utilize the vertical dimension above active regions, improving routing connectivity while maintaining high fill ratio as cells can be placed side-by-side without dedicated routing corridors.
Solution Approach 2:
The patent applies different routing strategies to different regions: global routing channels are routed over PMOS active regions while VDD and ground power rails are positioned between the routing channels and semiconductor layer. This localized differentiation allows each region to serve its specific function optimally, with PMOS regions serving dual purposes for both active器件 and global routing.
2Adaptability or versatility
If global routing channels are introduced to improve routing feasibility, then routing connectivity is improved, but chip size increases
Solution Approach 1:
The patent merges the function of global routing channels with the active regions of standard cells. By routing channels over PMOS active regions, the same physical space serves dual purposes: housing active器件 and providing routing pathways. This consolidation eliminates the need for separate routing corridors, reducing overall chip area while maintaining routing connectivity.
Solution Approach 2:
The invention utilizes the vertical dimension above active regions for routing, allowing standard cells to be placed closer together in the planar dimension. This three-dimensional spatial utilization reduces the two-dimensional chip footprint while providing adequate routing space.
3Adaptability or versatility
If global routing channels are introduced to improve routing feasibility, then routing connectivity is improved, but circuit speeds decrease
Solution Approach 1:
The patent positions VDD and ground power rails between the global routing channels and the semiconductor layer, creating localized power delivery paths that are optimized for speed. This separation ensures that power rails are not obstructed by routing channels, maintaining short and efficient power delivery paths to standard cells.
Solution Approach 2:
By routing global channels over active regions rather than between cells, the patent reduces the length of inter-cell routing paths. This spatial reconfiguration shortens signal propagation distances, improving circuit speeds despite the presence of global routing channels.
Data Source
AI summary
An integrated circuit chip includes CMOS integrated circuit cells arranged in a semiconductor layer, each including first and second active regions, having first and second polarities, respectively. A first power rail is routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions. A second power rail is routed over second active regions. Global routing channels are routed over the second active regions such that the second power rail is disposed between the global routing channels and the first power rail. The global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip.