Routing Grid Balancing Mask Misalignment Multi-Patterning

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in IC fabrication due to mask misalignment in multiple patterning lithography, which leads to variations in capacitive coupling, causing timing issues and performance degradation in integrated chips.

Innovation Solution

A method is introduced to balance the effects of mask misalignment by defining a routing grid with alternating colored grid lines for double patterning layers, where shapes are routed in a stair-step pattern to statistically average spacing variations, thereby reducing capacitive coupling variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple patterning lithography is used to print features smaller than the wavelength threshold, then manufacturing precision is improved, but mask misalignment occurs causing capacitive coupling variations

Engineering Contradiction:

Improvefeature size precisionVSAvoidcapacitive coupling consistency

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The IC layout is divided into multiple color groups (e.g., black and gray) where each color corresponds to a separate photomask. This segmentation allows features smaller than the wavelength threshold to be printed by distributing them across multiple masks, while the routing grid ensures that misalignment effects are balanced across different color groups

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the routing grid are assigned different colors based on their spatial position and alignment characteristics. By locally optimizing color assignments, the system ensures that adjacent features with different colors experience balanced misalignment effects, reducing capacitive coupling variations in specific critical regions

Inventive Principle:

Principle #3Local quality

2Device complexity

If mask misalignment is present in double patterning lithography, then manufacturing complexity is reduced, but timing issues and performance degradation occur

Engineering Contradiction:

Improvepatterning process complexityVSAvoidchip timing performance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent converts the harmful effect of mask misalignment into a beneficial outcome by using the routing grid to deliberately create alternating color patterns. This ensures that misalignment effects are statistically balanced, transforming the potential performance degradation into a controlled design feature that maintains timing consistency across the chip

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Manufacturing precision

If features are separated into different photomasks to print below printable threshold, then manufacturing precision is improved, but overlay error increases

Engineering Contradiction:

Improveminimum feature sizeVSAvoidoverlay alignment accuracy

Core Design Contradiction:

Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The routing grid is designed to create equipotential regions where the misalignment effect is balanced. By assigning colors based on the routing grid pattern, adjacent features experience equal and opposite misalignment shifts, effectively creating a neutral field where overlay errors cancel each other out, maintaining precise feature spacing despite mask misalignment

Inventive Principle:

Principle #12Equipotentiality

Data Source

PatentUS8709684B2Automatic misalignment balancing scheme for multi-patterning technology

Publication Date: 2014.04.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.