Routing Layer Re-optimization for IC Timing and Congestion
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Solution Overview
Problem
Existing routing layer assignment in VLSI digital design is inefficient due to varying optimization environments, leading to sub-optimal timing quality of result (QOR) and routing congestion, especially as design sizes grow and technology shrinks, causing inefficiencies in resource utilization and timing critical regions to shift.
Innovation Solution
The method involves identifying congested regions in integrated circuit designs, demoting selected nets from upper to lower routing layers, and employing low-cost optimizations to improve timing and reduce congestion, allowing for more efficient resource usage and timing recovery while controlling congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If routing layer assignment is performed early in physical synthesis, then initial routing structure is established, but timing quality of result deteriorates due to sub-optimal layer assignments and routing congestion
Solution Approach 1:
The patent implements dynamic routing layer re-optimization at the end point of physical design synthesis, allowing the routing structure to be adjusted and refined after initial placement and routing. This dynamic approach enables the system to adapt to changing timing requirements and congestion patterns, improving timing quality while managing routing complexity through iterative optimization rather than static early assignment
Solution Approach 2:
The patent changes the timing parameter optimization focus at the end point of physical synthesis, shifting from early structural routing to late-stage timing-driven layer re-assignment. This parameter change allows selective re-assignment of nets to different routing layers based on final timing analysis, improving timing quality of result while maintaining routing structure integrity
2Reliability
If multiple optimization objectives are pursued simultaneously, then comprehensive design optimization is achieved, but routing layer assignment efficiency deteriorates due to conflicting optimization criteria
Solution Approach 1:
The patent segments the optimization process into distinct phases: initial routing layer assignment during physical synthesis, and subsequent re-optimization at the end point. This segmentation allows different optimization objectives to be addressed at appropriate stages, with the final phase focusing specifically on timing quality improvement without the complexity of simultaneous multi-objective optimization, thereby improving both reliability and productivity
Solution Approach 2:
The patent performs preliminary routing layer assignment during the main physical synthesis flow, establishing an initial routing structure that can be later refined. This preliminary action allows the end-point re-optimization to focus specifically on timing improvements without having to simultaneously manage all routing decisions, thus improving routing layer assignment efficiency while achieving comprehensive optimization
Data Source
AI summary
To increase the efficiency of electronic design automation, at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identify at least one congested region in the putative integrated circuit design. Identify those of the nets of the putative integrated circuit design traversing through the at least one congested region, to obtain a plurality of candidate nets for demotion. Demote a plurality of selected nets, selected from the plurality of candidate nets for demotion, from an upper routing layer of the putative integrated circuit design to a lower routing layer of the putative integrated circuit design. At least some of the plurality of selected nets experience a loss of timing quality of result after the demoting.