Routing Layer Stress Buffering in Semiconductor Die
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Solution Overview
Problem
Semiconductor dies face challenges in increasing the number of routing traces without compromising signal integrity and protecting dielectric layers from thermal and mechanical stress, particularly with smaller bump-pads required for newer devices and brittle dielectric materials.
Innovation Solution
A semiconductor die design featuring smaller bump-pads with conductive traces that pass proximate to the bump-pads without contacting them, forming a stress buffering zone to reinforce the routing layer and absorb mechanical and thermal stress, allowing for increased routing density and improved signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of routing traces is increased to improve routing density, then signal integrity deteriorates due to increased trace resistance and capacitance
Solution Approach 1:
The patent introduces a vertical dimension by routing traces beneath the bump-pad structure through via holes in the dielectric layer. This allows traces to pass under bump-pads without making lateral contact, enabling higher routing density while maintaining signal integrity by avoiding the capacitive coupling that would occur with surface-level trace-bump-pad intersections.
2Productivity
If smaller bump-pads are used to increase routing density, then mechanical stress protection deteriorates
Solution Approach 1:
The patent performs preliminary stress distribution by routing traces to pass beneath bump-pads before solder balls are attached. This pre-positioned trace routing creates a stress buffer zone that absorbs and distributes mechanical stress from the solder balls, protecting the dielectric layer and smaller bump-pads from stress-related failures.
Solution Approach 2:
The trace structure acts as an intermediary element between the bump-pad and the underlying dielectric layer. By routing traces beneath the bump-pad, the system creates a buffer zone that mediates the transmission of mechanical stress, protecting the dielectric layer from direct stress exposure while maintaining electrical connectivity.
3Productivity
If traces are routed close to bump-pads to increase routing density, then stress protection deteriorates due to lack of buffer zone
Solution Approach 1:
The patent resolves the contradiction by moving traces from the lateral plane to the vertical dimension, routing them beneath the bump-pad through via holes. This allows traces to be physically close to bump-pads for high routing density while simultaneously creating a buffer zone that protects against thermal and mechanical stress.
Data Source
AI summary
A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.