Molded and Integrated Routing Layers for FOWLP Yield Stability
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Solution Overview
Problem
In the semiconductor device industry, challenges such as yield loss due to die drift, mold cure shrinkage, and warpage occur when manufacturing smaller and thinner devices, particularly in fan-out wafer level packaging (FOWLP), which complicates the routing of signals, power, and ground connections to the ball grid array pin or solder ball.
Innovation Solution
The implementation of a fan-out wafer level packaging process that involves forming semiconductor devices on a wafer level carrier, using pillars and encapsulants to create integrated routing layers, and subsequently singulating individual devices while breaking down routing into separate layers with different interconnect pitches, allowing for improved manufacturing efficiency and yield without increasing device thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fan-out wafer level packaging is used to create smaller and thinner devices, then device size and thickness are reduced, but yield loss occurs due to die drift, mold cure shrinkage, and warpage
Solution Approach 1:
The patent segments the routing process into multiple redistribution metal layers (first, second, and third redistribution metal layers) with different interconnect pitches. This segmentation allows each layer to be optimized independently, reducing the cumulative effect of manufacturing defects and improving overall yield while maintaining small device form factor.
Solution Approach 2:
The patent introduces vertical dimensionality by stacking multiple redistribution metal layers at different heights above the semiconductor die. This multi-layer approach distributes routing complexity across three dimensions, reducing warpage and shrinkage effects in any single layer while maintaining compact device footprint.
2Adaptability or versatility
If multiple layers of redistribution metal are required to route signals, then routing capability is improved, but manufacturing complexity and yield loss increase
Solution Approach 1:
The patent applies local quality by using different interconnect pitches for different redistribution metal layers. The first redistribution metal layer uses a first pitch, the second layer uses a second pitch, and the third layer uses a third pitch. This allows each layer to be optimized for its specific routing requirements, improving overall routing capability while managing manufacturing complexity through localized optimization.
3Reliability
If multiple layers of redistribution metal are used to route power and ground, then electrical connectivity is improved, but process complexity and cost increase
Solution Approach 1:
The patent uses multiple redistribution metal layers to simultaneously route signals, power, and ground connections. Each layer serves multiple functions, with conductors configured to provide signal routing, power distribution, and ground references. This multi-functional approach improves electrical connectivity reliability while managing process complexity through integrated design.
Data Source
AI summary
A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.