Semiconductor Routing Patch With Lateral Interconnect Offset
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in achieving high routing density and cost-effectiveness, particularly in smaller form factors where traditional silicon or glass interposers are costly and inefficient due to their thickness and lossy nature, limiting the miniaturization and integration of complex electronic devices.
Innovation Solution
A semiconductor package with a silicon-less integrated module (SLIM) high routing density patch, comprising alternating layers of metal and inorganic dielectric materials for the BEOL portion and organic dielectric materials for the RDL portion, bonded to a substrate with lower routing density, providing dense interconnects without the use of semiconductor materials and enabling thinner, more efficient interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional silicon or glass interposers are used, then electrical interconnection is achieved, but routing density is limited and cost increases due to thickness and material requirements
Solution Approach 1:
The patent extracts the semiconductor material (silicon) from the interposer structure, creating a silicon-less interposer that uses only dielectric and metal layers. This extraction eliminates the need for thick semiconductor substrates while maintaining routing functionality, thereby increasing routing density without proportionally increasing thickness
Solution Approach 2:
The patent transitions from planar routing in traditional interposers to three-dimensional vertical stacking of metal layers within the dielectric structure. This dimensional change enables significantly higher routing density by utilizing the vertical dimension for multiple signal layers, effectively increasing interconnection capacity without increasing the horizontal footprint
2Reliability
If traditional silicon or glass interposers are used, then electrical interconnection is achieved, but cost increases due to material usage and manufacturing complexity
Solution Approach 1:
The patent replaces expensive semiconductor materials (silicon, glass) with cheaper dielectric materials for the interposer structure. The metal layers serve as both structural and functional elements, eliminating the need for costly semiconductor substrate processing while maintaining reliable electrical interconnection through the metal-dielectric-metal stack
Solution Approach 2:
The patent employs composite material structures combining dielectric layers (for insulation and mechanical support) with metal layers (for electrical conduction). This composite approach allows optimization of each material for its specific function, achieving reliable electrical interconnection while reducing overall material cost compared to traditional homogeneous semiconductor interposers
3Volume of moving object
If thinner interconnects are used to reduce package size, then miniaturization is achieved, but routing density requirements become more challenging to meet
Solution Approach 1:
The patent resolves the conflict between miniaturization and routing density by exploiting the vertical dimension through multiple stacked metal layers. This allows the horizontal package footprint to be reduced while compensating for lower in-plane routing capacity by increasing the number of routing layers vertically, thereby maintaining high total routing density in a smaller overall volume
Data Source
AI summary
Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.