Routing Scheme for Heterogeneous Interconnected-Chip Networks
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Solution Overview
Problem
Conventional routing schemes in heterogeneous interconnected-chip networks experience significant latency when writing to or reading from multi-terabyte memories.
Innovation Solution
A routing scheme that includes parallel processing units with ICN controllers and routing tables, which identify memory spaces in multiple devices, allowing for efficient data transfer by individually addressing each memory space of equal size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional routing scheme with routing tables is used in a heterogeneous interconnected-chip network, then data can be transferred between different chips, but the latency for writing to or reading from multi-terabyte memory becomes substantial
Solution Approach 1:
The patent segments the multi-terabyte memory space into multiple smaller memory spaces, each with its own routing entry. Instead of managing a single large memory space with complex routing, the system divides it into manageable segments that can be accessed more efficiently, reducing the overall latency for data transfer operations.
Solution Approach 2:
The patent introduces a new dimension to the routing table structure by adding memory space identifiers that enable parallel access paths. This dimensional expansion allows the routing system to handle multiple memory spaces simultaneously, effectively reducing latency through parallel processing of data transfer operations.
2Productivity
If memory spaces are individually addressed with equal size, then data transfer efficiency is improved, but the routing table requires more addresses and memory
Solution Approach 1:
The patent merges the addressing of multiple equal-sized memory spaces into a unified routing table structure. By combining the address spaces and using a systematic addressing scheme, the system reduces the total memory required for routing tables while maintaining efficient individual access to each memory space.
Solution Approach 2:
The patent changes the addressing parameters by using equal-sized memory spaces with standardized address formats. This parameter standardization allows for more compact routing table representations and enables efficient parallel access patterns that improve data transfer efficiency without proportionally increasing routing table memory requirements.
Data Source
AI summary
The time required to read from and write to multi-terabyte memory chips in an inter-chip network can be reduced by breaking each memory chip into a number of memory spaces, and then individually addressing each memory space with an address that identifies the memory space, a line number within the memory space, and a number of transmit/receive ports to be used to access the line number.