Deep Sub-Micron Routing Segmentation for Yield
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Solution Overview
Problem
In deep sub-micron semiconductor manufacturing, existing routing methods face challenges with irregular metal shapes and non-planar wire structures, leading to reduced manufacturing yield due to optical effects and increased complexity, which current technologies like EP 0 982 774 do not adequately address.
Innovation Solution
A method is introduced where wide signal nets are decomposed into parallel narrow wire segments during the design phase, which are then rejoined at the source and sink, allowing for additional wires in empty tracks while maintaining electrical properties, and replicating wires with high aspect ratios to enhance uniformity and redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wide wires are used to meet current density and electro-migration requirements, then electrical performance is improved, but wireability deteriorates due to consumption of additional wiring channels
Solution Approach 1:
The patent segments wide wires into multiple narrow parallel wires (e.g., a 2.4u wide wire divided into four 0.6u wide wires). This segmentation maintains the equivalent current carrying capacity and electro-migration resistance of the original wide wire while enabling better routing flexibility and adherence to design rules that limit maximum wire width in deep sub-micron technologies.
2Device complexity
If wide wires are decomposed into narrower wires, then wireability is improved, but manufacturing precision deteriorates due to irregular metal shapes and optical effects
Solution Approach 1:
The patent applies different wire width qualities to different routing contexts. In regions where routing flexibility is needed, narrow segmented wires are used. In regions where manufacturing precision is critical, the patent introduces fill patterns (such as cheese patterns or solid fills) to create uniform metal density and regular geometries, thereby improving optical lithography results and reducing manufacturing defects.
Solution Approach 2:
The patent changes the physical parameters of the wire structure by introducing fill patterns that modify metal density and geometry. These fill patterns transform irregular wire shapes into more regular structures with uniform dimensions, improving the performance of optical lithography processes and reducing manufacturing yield losses associated with irregular metal shapes.
3Manufacturing precision
If regular metal structures are created to improve manufacturing yield, then manufacturing precision is improved, but device complexity increases due to inability to connect pins without creating unwanted connections
Solution Approach 1:
The patent performs preliminary routing actions during the design phase where wide wires are decomposed into narrow segments and appropriate fill patterns are pre-placed. This preliminary structuring creates a framework that guides subsequent routing operations, enabling regular metal structures to be formed while avoiding unwanted connections between pins through careful placement of segments and fills before final routing completion.
Data Source
AI summary
A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore manufacturability of metal interconnect layers. The decomposition step is performed during a preliminary wire route after initial physical placement. Access to pin shapes is ensured through a branching and a recombination of the parallel single-width wires. Separate wire segments are rejoined at the source and sink of the net. The parallel wire segments do not change the logic behavior of the circuit.