Routing Substrate Second Power Plane Reduces Interconnect Inductance
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Solution Overview
Problem
Integrated circuits (ICs) face performance losses due to increased inductance in signal routing paths, particularly when capacitors are laterally offset from the IC package, leading to longer signal routing paths and higher interconnect inductance, which affects decoupling capacitance and power integrity.
Innovation Solution
A routing substrate with additional metallization layers and a second power plane disposed in a dielectric layer between adjacent metal layers reduces the dielectric thickness, minimizing interconnect inductance and allowing for more flexible capacitor placement, including horizontal routing paths without increasing the overall height of the IC package or circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the capacitor is mounted laterally offset from the die, then the routing substrate can accommodate more flexible capacitor placement, but the signal routing path length increases and interconnect inductance increases
Solution Approach 1:
The patent introduces an additional metallization layer between adjacent metal layers to create a new routing dimension. This allows the signal path to route through the intermediate dielectric layer, effectively adding a spatial dimension for signal transmission and enabling shorter paths despite lateral capacitor placement.
Solution Approach 2:
The routing substrate is segmented into multiple metallization layers with dielectric layers between them. This segmentation allows signals to be routed through different layers and via holes, creating multiple possible signal paths and enabling optimization of the shortest path even when capacitors are laterally offset.
2Strength
If the dielectric layer thickness is increased, then the routing substrate can provide better insulation and structural integrity, but the interconnect inductance increases
Solution Approach 1:
By adding another metallization layer in between, the patent creates a new spatial arrangement where the dielectric layer thickness can be optimized independently. The signal path can traverse the intermediate dielectric layer through via holes, allowing the overall structure to maintain insulation while the signal path length through the dielectric is minimized.
Solution Approach 2:
The patent changes the parameter of dielectric layer thickness by introducing an intermediate dielectric layer between adjacent metal layers. This allows the dielectric thickness to be controlled and optimized to balance insulation requirements with inductance minimization, as the signal path can be routed through this controlled-thickness dielectric via holes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces interconnect inductance, mitigates performance losses, and provides flexibility in capacitor placement, enhancing signal processing and power integrity by minimizing the impact of longer signal routing paths.
Implementation Method 1
there is a flux loop created between the adjacent metal layers when power signals are carried in power planes in the adjacent metal layers
Data Source
AI summary
Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.