Routing Switching Device Data Caching Method

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Solution Overview

Problem

The increasing port speed and varying data packet lengths in routing and switching devices complicate timing control, leading to suboptimal bandwidth utilization in data caching, particularly due to irrelevant read and write operation addresses and unequal data slice lengths.

Innovation Solution

A routing and switching device with a caching control module and data caching list module that writes and reads data slices in continuous burst operations, optimizing storage by filling contiguous address spaces and updating caching states, ensuring efficient bandwidth utilization through direct hardware management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data slices are stored in exterior cache with dynamic queue storage areas, then storage flexibility is improved, but bandwidth utilization rate deteriorates due to scattered address patterns

Engineering Contradiction:
Improvestorage flexibilityVSAvoidbandwidth utilization rate
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent segments the data packet into data slices and stores them in continuous address spaces within the exterior cache. By dividing the data packet and placing slices in contiguous memory locations rather than scattered queue storage areas, the system achieves both flexibility in handling variable packet lengths and optimal bandwidth utilization through continuous memory access patterns.

Inventive Principle:
Principle #1Segmentation

2Productivity

If port speed increases and data packet length varies, then data transmission capacity is improved, but timing control complexity increases

Engineering Contradiction:
Improvedata transmission capacityVSAvoidtiming control complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic timing control mechanisms that adapt to varying port speeds and data packet lengths. The system dynamically adjusts cache management parameters and timing sequences based on actual transmission conditions, allowing high-speed operation with variable packet sizes without overwhelming complexity in the control logic.

Inventive Principle:
Principle #15Dynamics

3Productivity

If read and write operation addresses are made irrelevant for optimization, then caching efficiency is improved, but address management complexity increases

Engineering Contradiction:
Improvecaching efficiencyVSAvoidaddress management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the address management functions into a unified continuous address space mechanism. By consolidating read and write address handling into a single continuous memory region rather than separate managed address spaces, the system achieves simplified address management while maintaining high caching efficiency through predictable continuous access patterns.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9025608B2Route switching device and data cashing method thereof
Publication Date: 2015.05.05 ZTE CORP
  • US9025608B2 patent drawing
  • US9025608B2 patent drawing
  • US9025608B2 patent drawing

AI summary

The present invention discloses a routing and switching device and a data caching method thereof. The method includes: a routing and switching device, when receiving a data packet, and if the routing and switching device inquires that a data caching state of an exterior cache is that there are data slice row addresses not fully filled and continuous space in the data slice row addresses not fully filled is enough to store all the data slices of the data packet, then writing all the data slices of the data packet into the data slice row addresses not fully filled, storing packet information of the data packet and the written data slice row addresses, and updating the data caching state of the exterior cache. The present invention enhances the utilization rate of the memory bandwidth. In addition, the present invention is also easy to be applied in other relevant data caching managements.