Roving Memory Region Write Paths for Heterogeneous Flash Storage
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Solution Overview
Problem
Modern data storage systems face inefficiencies in data reliability and access schemes when dealing with heterogeneous types and sizes of storage class and non-storage class memory, leading to sub-optimal operations with different types of data and metadata.
Innovation Solution
The proposed storage systems optimize write paths by selecting from multiple modes, including writing to non-storage class memory and bypassing it, using mirrored RAID formats, parity-based RAID formats, and direct writes to storage class memory, with mechanisms for handling metadata and heterogeneous memory configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single data reliability scheme and data access scheme are used for all types of data and memory configurations, then the system structure is simple, but the data access efficiency is sub-optimal for different types of data and heterogeneous memory
Solution Approach 1:
The patent implements dynamic selection of data reliability schemes and data access schemes based on the type of data being stored and the specific memory configuration. The system can adaptively choose between different RAID schemes (RAID 0, 1, 5, 6, 10, 50, 60) and different access patterns (sequential access, random access, mirrored access) to optimize performance for each workload, transforming a static single-scheme system into a dynamic multi-scheme system that adapts to changing requirements
Solution Approach 2:
The system changes operational parameters (data reliability scheme selection, data access scheme selection) based on input conditions (data type, memory configuration). Different parameters are selected for different scenarios: sequential access for metadata, random access for data, mirrored RAID for high-reliability requirements, and parity-based RAID for capacity-efficient scenarios, allowing optimization across multiple dimensions
2Productivity
If multiple data reliability schemes and data access schemes are implemented for different data types and memory configurations, then data access efficiency is optimized, but the system complexity increases
Solution Approach 1:
The patent segments the storage system into distinct functional components: metadata storage region, data storage region, multiple memory devices with different characteristics, and separate control logic for selecting reliability and access schemes. This segmentation allows each component to be optimized independently while working together as an integrated system, managing complexity through modular organization
Solution Approach 2:
The system implements a universal controller that can select and switch between multiple data reliability schemes and data access schemes based on the workload requirements. This multi-functional controller handles different data types (metadata, data), different memory configurations (homogeneous, heterogeneous), and different access patterns through a single unified architecture, avoiding the need for separate dedicated systems for each scenario
3Speed
If non-storage class memory is used for data buffering, then write speed is improved, but data reliability may be compromised without proper redundancy schemes
Solution Approach 1:
The patent introduces non-storage class memory as an intermediary component between the host and storage class memory. This intermediary provides high-speed write buffering while working in conjunction with storage class memory that provides persistence and reliability. The system can write data quickly to non-storage class memory first, then asynchronously transfer to storage class memory with appropriate redundancy, decoupling the speed requirement from the reliability requirement
Solution Approach 2:
The system implements beforehand cushioning by using non-storage class memory as a protective buffer that absorbs write operations. This buffer provides a cushion against direct writes to slower, more reliable storage class memory, allowing the system to maintain high write speeds while the redundancy schemes in storage class memory provide the reliability cushion. The non-storage class memory cushions the impact of high-speed writes on the overall system reliability
Data Source
AI summary
A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.