Row Activation-Biased Caching for DRAM Row Hammer Mitigation
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Solution Overview
Problem
Conventional row hammer detection techniques in DRAM devices are probabilistic and cannot guarantee perfect prevention of data corruption, making them vulnerable to attacks that exploit their weaknesses, leading to data corruption issues due to frequent row activations.
Innovation Solution
A row hammer detector integrated into a memory controller with a cache memory that implements a row activation-biased caching policy, using counters to track row activations and initiate refresh commands when thresholds are exceeded, ensuring perfect tracking and mitigation of row hammer attacks while being energy and space efficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional probabilistic row hammer detection techniques are used, then device complexity is reduced, but reliability of row hammer prevention deteriorates
Solution Approach 1:
The detection system is segmented into multiple independent components: a row hammer detector that monitors row activations, a cache memory that stores data, and a controller that coordinates between them. This segmentation allows each component to have a specialized function, improving overall reliability while managing complexity through modular design
Solution Approach 2:
A cache memory is introduced as an intermediary between the memory media and the processor. The cache stores copies of frequently accessed data, allowing the system to detect and mitigate row hammer attacks by monitoring row activation patterns in the cache without directly interfering with the main memory operations, thus improving detection reliability
2Reliability
If deterministic row hammer tracking is implemented, then reliability of data integrity is improved, but use of energy increases
Solution Approach 1:
Instead of deterministically tracking every single row activation in the entire memory, the system applies partial tracking by focusing only on rows that are likely to be victims of row hammer attacks. The cache memory naturally filters which rows need monitoring, reducing energy consumption while maintaining data integrity for critical rows
Solution Approach 2:
The cache memory structure itself provides row hammer mitigation capabilities without requiring additional active monitoring for all rows. By leveraging the existing cache replacement policies and row activation patterns, the system achieves deterministic protection for cached data while consuming less energy than a comprehensive deterministic tracking system would require
3Measurement precision
If row activation monitoring is continuously performed, then measurement precision of row hammer detection is improved, but loss of energy increases
Solution Approach 1:
The system performs row activation monitoring periodically rather than continuously for all rows. The cache memory structure allows the system to check row activation counts at relevant intervals (when cache lines are accessed or replaced), maintaining measurement precision for detected rows while reducing overall energy consumption by not continuously monitoring every row in memory
4Productivity
If cache memory with row activation bias is used, then productivity of row hammer detection is improved, but device complexity increases
Solution Approach 1:
The cache memory serves multiple functions simultaneously: it acts as a standard cache for improving processor performance, a row hammer detector for security, and an energy-efficient storage buffer. By making the cache multi-functional, the system improves detection productivity without adding separate dedicated detection hardware, thus managing complexity through functional consolidation
Data Source
AI summary
A cache memory having a memory media device row activation-biased caching policy is described. The cache policies that are biased based on row activation counts include at least one of a cache line eviction policy which determines which cache lines are the most evictable from the cache memory, and cache line storage policy which determined which row data is allocated cache lines for storage. A memory controller including a row activation-biased cache memory is also described. The memory media device may be DRAM.