3D NAND Memory Program-Verify With Row-Adaptive Sense Time
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in achieving well-defined threshold voltage distributions and high error rates during programming, particularly due to variations in programming speeds across different regions of the memory cells.
Innovation Solution
Implementing adaptive sense time techniques for memory cells based on their location, such as using longer sense times for cells in edge rows or farther from the word line driver, and incorporating a Verify Low (VL) step with extended sensing to ensure accurate programming near target threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform sense time is used for all memory cells during programming, then the programming process is simple to control, but programming errors increase due to variations in programming speeds across different regions
Solution Approach 1:
The patent applies different sense time values to different groups of memory cells based on their physical location. Specifically, memory cells in edge rows are assigned a first sense time value, while memory cells in non-edge rows are assigned a second sense time value. This local differentiation compensates for variations in programming speeds across different regions of the memory array, thereby improving programming accuracy without requiring a completely complex control mechanism.
Solution Approach 2:
The patent segments the memory array into different groups based on row location (edge rows versus non-edge rows). By dividing the memory cells into distinct groups and applying different sense time parameters to each group, the system can address the programming speed variations more effectively than a uniform approach, while maintaining manageable control complexity through systematic categorization.
2Reliability
If longer sense times are used for all memory cells to ensure accurate programming, then programming accuracy improves, but programming time increases
Solution Approach 1:
Instead of applying a uniformly long sense time to all memory cells, the patent applies longer sense times only to specific groups of memory cells that require it (such as edge rows), while using shorter sense times for other groups (non-edge rows). This localized approach ensures programming accuracy where needed while minimizing the overall programming time penalty.
Solution Approach 2:
The patent applies the extended sense time action only partially - specifically to memory cells in edge rows that benefit most from it - rather than applying it excessively to all memory cells. This selective application achieves the necessary programming accuracy for problematic regions without incurring the full time cost across the entire memory array.
3Manufacturing precision
If adaptive sense time based on row location is implemented, then programming accuracy improves with narrow threshold voltage distributions, but control complexity increases
Solution Approach 1:
The patent implements adaptive sense time control by assigning different sense time values to different groups of memory cells based on their row location. Memory cells in edge rows receive one sense time value while memory cells in non-edge rows receive another value. This local differentiation achieves narrow threshold voltage distributions and high programming precision without requiring overly complex control mechanisms.
Solution Approach 2:
The patent segments the memory array into distinct groups (edge rows and non-edge rows) and applies different sense time parameters to each segment. This systematic segmentation enables precise control over threshold voltage distributions while maintaining manageable control complexity through clear, rule-based categorization and parameter assignment.
Data Source
AI summary
Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.