Row Address Converter for Memory Section Replacement
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Solution Overview
Problem
As memory devices increase in size and complexity, traditional repair schemes for addressing failures become increasingly difficult, leading to slower operation and increased complexity due to the need for more redundant rows and columns, which can complicate data access and slow down memory device performance.
Innovation Solution
A row addressing scheme that employs a row address converter to map external addresses to internal addresses, enabling simplified section replacement and reducing the complexity of block repair schemes by using address mapping prior to section replacement detection, thereby increasing the speed of the redundant row activation path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of redundant rows and columns is increased to account for more expected failures in larger memory arrays, then the reliability is improved, but the device complexity increases and the memory speed decreases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank containing sections that can be independently replaced. This segmentation allows repair schemes to be applied locally rather than globally, reducing overall device complexity while maintaining reliability through targeted redundancy management.
Solution Approach 2:
The patent introduces a new dimension to address mapping by implementing bank-specific address conversion logic. Instead of a single global address mapping system, each bank has its own address conversion mechanism, which simplifies the overall addressing complexity while enabling effective use of redundant rows and columns across the expanded memory array.
2Reliability
If the number of redundant rows and columns is increased to account for more expected failures in larger memory arrays, then the reliability is improved, but the memory speed decreases
Solution Approach 1:
By segmenting the memory into banks with independent address conversion, the system can process address translations in parallel across different banks, improving memory access speed while maintaining the redundancy needed for reliability.
Solution Approach 2:
Address conversion is performed as a preliminary action within each bank before data access occurs. This pre-processing of addresses within localized banks reduces the critical path delay compared to global address mapping, thereby improving memory speed while preserving reliability through maintained redundancy ratios.
3Reliability
If traditional repair schemes are used with larger memory arrays, then the reliability is maintained, but the addressing complexity increases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank containing sections that can be independently replaced. This segmentation allows repair schemes to be applied locally rather than globally, reducing overall device complexity while maintaining reliability through targeted redundancy management.
Solution Approach 2:
The patent introduces a new dimension to address mapping by implementing bank-specific address conversion logic. Instead of a single global address mapping system, each bank has its own address conversion mechanism, which simplifies the overall addressing complexity while enabling effective use of redundant rows and columns across the expanded memory array.
Data Source
AI summary
Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2^n number of normal rows and mapping the row address to a redundant row address by subtracting a value from the row address.