Row Arbiter Tree for High-Speed Neural Spike Signal Transmission
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Solution Overview
Problem
Current neural network-based electronic devices face limitations in integrating a large number of neurons due to area and power consumption issues, leading to decreased transmission speed of spike signals when using conventional address-event-representative (AER) circuits that serialize parallel spike signals.
Innovation Solution
An electronic device with a high-speed interface that includes a neuron array, a row address encoder, and a row arbiter tree with multiple arbiters and latches to arbitrate and store states, allowing for parallel transmission of spike signals through multiple paths, thereby maintaining the order and speed of signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional AER circuits are used to serialize parallel spike signals, then area and power consumption are reduced, but transmission speed decreases
Solution Approach 1:
The interface circuit is segmented into multiple independent arbitration paths (first path, second path, etc.), each capable of handling spike signals from different neuron rows simultaneously. This segmentation allows parallel processing of multiple spike signals without requiring a single complex serialization circuit, thereby maintaining high transmission speed while managing device complexity through modular design.
Solution Approach 2:
The patent transitions from a single-dimension serialization approach to a multi-dimensional parallel arbitration structure. By introducing multiple arbitration paths that operate simultaneously in different dimensions (spatial parallelism), the system achieves high-speed transmission without proportionally increasing overall circuit complexity, as each path can be independently optimized and managed.
2Productivity
If multiple neurons are integrated in one semiconductor chip, then neural network performance is improved, but area and power consumption limitations arise
Solution Approach 1:
The neuron array is organized into multiple rows, each with its own address encoder and arbitration path. This segmentation allows the chip to integrate many neurons by dividing them into manageable rows, reducing the area required per neuron while maintaining overall neural network processing capability through parallel row operations.
Solution Approach 2:
The arbitration circuit structure is designed to be universal and scalable, where the same basic arbitration path can be replicated and configured for different numbers of neurons and rows. This multi-functionality allows the chip to adapt to various neural network sizes and configurations without requiring completely different circuit designs, optimizing area utilization.
3Speed
If spike signals from multiple rows are transmitted in parallel, then transmission speed is improved, but signal distortion increases
Solution Approach 1:
The address encoders for each row perform preliminary encoding of spike signals before transmission, and the arbitration paths maintain the temporal order of signals within each row. This preliminary organization ensures that even though signals travel in parallel, their relative timing and sequence information is preserved, preventing signal distortion and maintaining transmission reliability.
Solution Approach 2:
The row arbiter trees act as intermediary structures that receive, arbitrate, and forward spike signals from multiple rows to the output. These intermediaries ensure that parallel-transmitted signals are properly ordered and routed, maintaining signal integrity and preventing distortion while enabling high-speed parallel transmission.
Data Source
AI summary
Disclosed is an electronic device that supports a neural network including a neuron array including neurons, a row address encoder that receives spike signals from neurons and outputs request signals in response to the received spike signals, and a row arbiter tree that receives request signals from the row address encoder and outputs response signals in response to the received request signals. The row arbiter tree includes a first arbiter that arbitrates first and second request signals among request signals, a first latch circuit that stores a state of the first arbiter, a second arbiter that arbitrates third and fourth request signals among request signals, a second latch circuit that stores a state of the second arbiter, and a third arbiter that delivers a response signal to the first and second arbiters based on information stored in the first and second latch circuits.