Row-Based Cache Mapping for Sequential Access Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional row-based memory systems experience increased access latencies and fragmentation due to the need for repeated activations and precharges when handling sequentially accessed cache lines, especially with larger cache line sizes, which also reduce set associativity and increase power consumption.
Innovation Solution
Mapping sequentially addressed cache lines to the same row in the row-based cache, reducing the number of activations and precharges required, and using a tag array to efficiently manage and store these cache lines, thereby improving set associativity and reducing fragmentation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequentially addressed cache lines are stored in different rows, then row access operations are simpler, but the number of activations and precharges increases, leading to increased access latency and power consumption
Solution Approach 1:
The patent merges multiple sequentially addressed cache lines into the same cache row, allowing them to be accessed together with a single activation operation. This combining of cache lines that would traditionally require separate row activations reduces the total number of activations and precharges needed, thereby decreasing access latency and power consumption while managing complexity through systematic organization
2Productivity
If larger cache line sizes are used, then fewer cache lines are needed to store the same data, but set associativity is reduced and fragmentation increases
Solution Approach 1:
The patent segments the cache into multiple ways within each row, allowing each cache line to be placed in a specific way based on its address. This segmentation enables the cache to maintain high set associativity even with larger cache line sizes, as each way can independently store different cache lines. The systematic segmentation prevents fragmentation by providing multiple placement options for each cache line
3Speed
If multiple activations occur before precharge, then data access speed improves, but power consumption and memory bank availability decrease
Solution Approach 1:
The patent enables continuous data access within an activated row by allowing multiple cache line reads/writes without requiring precharge between operations. This continuity of useful action maintains high data access speed while reducing power consumption, as the row remains activated and available for subsequent accesses to other cache lines stored in the same row, eliminating the need for repeated activation-precharge cycles
Data Source
AI summary
The present disclosure relates to a method and system for mapping cache lines to a row-based cache. In particular, a method includes, in response to a plurality of memory access requests each including an address associated with a cache line of a main memory, mapping sequentially addressed cache lines of the main memory to a row of the row-based cache. A disclosed system includes row index computation logic operative to map sequentially addressed cache lines of a main memory to a row of a row-based cache in response to a plurality of memory access requests each including an address associated with a cache line of the main memory.